Information about the kinetics of PCR reactions is encoded in the amplification curve. However, in digital PCR (dPCR), this information is typically neglected by collapsing each amplification curve into a binary output (positive/negative). Here, we demonstrate that the large volume of raw data obtained from real-time dPCR instruments can be exploited to perform data-driven multiplexing in a single fluorescent channel using machine learning methods, by virtue of the information in the amplification curve. This new approach, referred to as amplification curve analysis (ACA), was shown using an intercalating dye (EvaGreen), reducing the cost and complexity of the assay and enabling the use of melting curve analysis for validation. As a case study, we multiplexed 3 carbapenem-resistant genes to show the impact of this approach on global challenges such as antimicrobial resistance. In the presence of single targets, we report a classification accuracy of 99.1% (N = 16188), which represents a 19.7% increase compared to multiplexing based on the final fluorescent intensity. Considering all combinations of amplification events (including coamplifications), the accuracy was shown to be 92.9% (N = 10383). To support the analysis, we derived a formula to estimate the occurrence of coamplification in dPCR based on multivariate Poisson statistics and suggest reducing the digital occupancy in the case of multiple targets in the same digital panel. The ACA approach takes a step toward maximizing the capabilities of existing real-time dPCR instruments and chemistries, by extracting more information from data to enable data-driven multiplexing with high accuracy. Furthermore, we expect that combining this method with existing probe-based assays will increase multiplexing capabilities significantly. We envision that once emerging point-of-care technologies can reliably capture real-time data from isothermal chemistries, the ACA method will facilitate the implementation of dPCR outside of the lab.

This paper presents a 32x32 ISFET array with inpixel dual-sensing and programmability targeted for on-chip DNA amplification detection. The pixel architecture provides thermal and chemical sensing by encoding temperature and ion activity in a single output PWM, modulating its frequency and its duty cycle respectively. Each pixel is composed of an ISFETbased differential linear OTA and a 2-stage sawtooth oscillator. The operating point and characteristic response of the pixel can be programmed, enabling trapped charge compensation and enhancing the versatility and adaptability of the architecture. Fabricated in 0.18µm standard CMOS process, the system demonstrates a quadratic thermal response and a highly linear pH sensitivity, with a trapped charge compensation scheme able to calibrate 99.5% of the pixels in the target range, achieving a homogeneous response across the array. Furthermore, the sensing scheme is robust against process variations and can operate under various supply conditions. Finally, the architecture suitability for on-chip DNA amplification detection is proven by performing Loop-mediated Isothermal Amplification (LAMP) of phage lambda DNA, obtaining a time-to-positive of 7.71 minutes with results comparable to commercial qPCR instruments. This architecture represents the first in-pixel dual thermo-chemical sensing in ISFET arrays for Lab-on-a-Chip diagnostics.

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This paper presents a novel ISFET architecture with in-pixel ADC for large-scale integration and on-chip computational capabilities. Each pixel is composed by a comparator connected to a set of memory elements, storing in-pixel each conversion. Using this sensing scheme, the entire frame of ISFET pixels is acquired and stored in one single ADC cycle, eliminating the need for global or column-level ADCs and making this architecture scalable to larger arrays without instrumentation overhead. To enable compensation of ISFET non-idealities such as trapped charge, a novel gate-bootstrapping mechanism is introduced, enhancing the ADC dynamic range without additional circuitry and accommodating a trapped charge compensation range of 4.45 V. Fabricated in standard 180nm CMOS technology, the system is composed by a 16x16 ISFET array, a global DAC and a Digital Control Unit that enables operation and off-chip communication. The entire frame is acquired in 51.2 µs with a pixel power consumption of 10.15 µW , while storing the result in-pixel and eliminating the need for off-chip memories.