Real-time blood glucose (BG) prediction can enhance decision support systems for insulin dosing such as bolus calculators and closed-loop systems for insulin delivery. Deep learning has been proven to achieve state-of-the-art performance in BG prediction. However, it is usually seen as a very computationally expensive approach, hence difficult to implement in wearable medical devices such as transmitters in continuous glucose monitoring (CGM) systems. In this work, we introduce a novel deep learning framework to predict BG levels with the edge inference on a microcontroller unit embedded in a lowpower system. By using glucose measurements from a CGM sensor and a recurrent neural network that builds on long-short term memory, the personalized models achieves state-of-the-art performance on a clinical data set obtained from 12 subjects with T1D. In particular, the proposed method achieves an average root mean square error of 19.10 ± 2.04 for a 30-minute prediction horizon (PH) and 32.61 ± 3.45 for a 60-minute PH with high clinical accuracy. Notably, the framework has been optimized to achieve a minimum use of hardware resources (34KB FLASH and 1KB SRAM) as well as an execution time of 22 ms for low power operations (8 µW). The presented system has the potential to be implemented in wearable medical devices for diabetes care (CGM and insulin pumps) and to be integrated within an Internet of Things platform.Index Terms-Diabetes, deep learning, artificial pancreas, Internet of things, microcontroller, edge inference, LSTM.

An ultra-high frame rate and high spatial resolution ion-sensing Lab-on-Chip platform using a 128 × 128 CMOS ISFET array is presented. Current mode operation is employed to facilitate high-speed operation, with the ISFET sensors biased in the triode region to provide a linear response. Sensing pixels include a reset switch to allow in-pixel calibration for nonidealities such as offset, trapped charge and drift by periodically resetting the floating gate of the ISFET sensor. Current mode row-parallel signal processing is applied throughout the readout pipeline including auto-zeroing circuits for the removal of fixed pattern noise. The 128 readout signals are multiplexed to eight high-sample-rate on-chip current mode ADCs followed by an off-chip PCIe-based readout system on a FPGA with a latency of 0.15 s. Designed in a 0.35 µm CMOS process, the complete system-on-chip occupies an area of 2.6 × 2.2 mm 2 with a pixel size of 18 × 12.5 µm 2 and the whole system achieves a frame rate of 3000 fps which is the highest reported in the literature for ISFET arrays. The platform is demonstrated in the application of real-time ion-imaging through the high-speed visualization of sodium hydroxide (NaOH) diffusion in water at 60 fps on screen in addition to slow-motion playback of ion-dynamics recorded at 3000 fps. Index Terms-ISFET, ultra-high frame rate, linearity conversion, current mode, in-pixel calibration. Junming Zeng (S'17) received the Bachelor degree with first class honors in Electronic Engineering from the University of Southampton, UK in 2016, and the Master degree with Distinction in Analogue and Digital Integrated Circuit Design from Imperial College London, UK in 2017. He is currently a PhD student with Centre for Bio-Inspired Technology, Department of Electrical and Electronic Engineering, Imperial College London UK. His research interests include Analogue and Mixed Signal IC design and digital system design for biomedical applications. Specifically, he is now working on designing a CMOS Labon-Chip ultra-high speed ion imaging platform. He is the recipient of the Department PhD Scholarship from Imperial College London, and the awardee of the Best Student Paper Award 1st Prize at ISCAS 2018. Lei Kuang received the B.Sc. degree in Industrial electronics and control engineering from the Liverpool John Moores University, Liverpool, UK in 2016 and the M.Sc. degree in embedded systems from the University of Southampton, Southampton, UK in 2017. Then, he spent one year working as an embedded system design engineer in China's IC industry for SoC IP design and FPGA development. He is currently working toward his second M.Sc. degree in analog and digital integrated circuit design at Imperial College London, London, UK. His interests include high-speed and low-power digital system design, image processing and algorithm acceleration on FPGAs.

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