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The model-based library (MBL) matching technique was applied to measurements of photoresist patterns exposed with a leading-edge ArF immersion lithography tool. This technique estimates the dimensions and shape of a target pattern by comparing a measured SEM image profile to a library of simulated line scans. In this study, a double trapezoid model was introduced into MBL library, which was suitable for precise approximation of a photoresist profile. To evaluate variously-shaped patterns, focus-exposure matrix wafers were exposed under three-illuminations. The geometric parameters such as bottom critical dimension (CD), top and bottom sidewall angles were estimated by MBL matching. Lithography simulation results were employed as a reference data in this evaluation. As a result, the trends of the estimated sidewall angles are consistent with the litho-simulation results. MBL bottom CD and threshold method 50% CD are also in a very good agreement. MBL detected wide-SWA variation in a focus series which were determined as in a process window by CD values. The trend of SWA variation, which is potentiality to undergo CD shift at later-etch step, agreed with litho-simulation results. These results suggest that MBL approach can achieve the efficient measurements for process development and control in advanced lithography.

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The transistor architecture of complementary FET (CFET) is attractive for scaling down in technology nodes beyond 1 nm. CFET comprising vertically stacked nMOS and pMOS can be integrated monolithically and sequentially. The monolithic process is cost effective but complex because it requires patterning of high-aspect-ratio (HAR) structures and vertical edge placement control for stacked n-p nanosheet channels. It also brings challenges to in-line metrology in measuring the vertical dimension. In this work, we demonstrate a non-destructive, in-line metrology solution to measure the etch-back depth by CD-SEM. As the backscattered electron (BSE) signal intensity at the bottom of an HAR structure is determined by the structure's depth and top dimension, the depth can be monitored via an index based on the grey level and top dimension in CD-SEM images. Wafers with different etch-back depths were measured for evaluation of the M0 etch-back process in CFET integration. Good agreement was obtained between the etch-back depths measured by CDSEM and TEM. The flexible capability of CD-SEM to measure the depth and variation from extremely small areas to the wafer level could be helpful for CFET process control.