Sensor interfaces need to be robust and accurate for many applications. This is more challenging for sensor systems operating in radiation environments because the mismatch between components grows as a result of the absorbed total ionizing dose (TID). In frequency-based sensor interfaces, the frequency drift of the voltage-controlled oscillator (VCO) can create dynamic output offset, gain, and linearity errors unless a calibration algorithm is included. In this paper, a digital intensive dynamic offset cancelation technique is proposed for an open loop VCO-based sensor to digital converter, which is achieved by making periodic adjustments to the average center biasing voltage of one of the VCOs in a differential architecture, in effect to make their center frequencies match. A simulation of the behavioral model of the proposed architecture was developed and hardware implementation of the whole system was performed on an FPGA by emulating, with digital modules, the characteristics of the two VCO outputs modulated with differential inputs. The results showed that the output offset error was reduced from around 5% to 0.1% for a relative oscillators’ drift close to 10% of the tuning range, and the SNDR is relatively maintained when subjected to variable relative VCO drifts.

Maintaining the accuracy of a sensor system across various operating conditions has always been a challenge, especially for those operating in harsh surroundings such as a radiation environment. Concerning frequency-based sensor interfaces, supply voltage drifts and gain shift of the voltage-to-frequency converter (VFC) are critical design issues. These manifest as gain, offset, and linearity errors at the system level and therefore require continuous correction mechanisms. In this paper, dynamic gain and offset error-compensated open-loop frequency-based sensor interface architectures with adaptive clock frequency are proposed, which result in a ratiometric digital output. To address the mismatch issue, two architectures, one with periodic swapping of the VFCs’ inputs and outputs, and the other with the use of a single analog-to-digital converter (ADC) as an analog front end, are developed. The concepts were demonstrated with implementations on a Zynq board (ZYBO). The results of the first architecture showed that for a 25% gain mismatch between the VFCs, the output gain error was reduced from around 7.4% to 0.79% and the offset error was reduced from around 11.8% to 0.01%. Additionally, for the second architecture, a maximum of 0.11% gain error and 0.1% offset error were recorded for an emulated ±25% supply drift.