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N-path techniques have become a popular candidate alternative to external pre-selection filtering in wireless receivers. Their main attraction lies in enabling tunable on-chip high-filters, with straightforward migration from one CMOS node to another. However, parasitic capacitance at the N-path filter input offsets the bandpass response from the desired center frequency in wideband circuits. In this paper, we focus on an LNA-first receiver and show that the offset at the LNA output varies in magnitude depending on LNA and filter load impedance properties. An offset-tuning approach is then evaluated for its effects on receiver gain and noise and to obtain design guidelines. We propose a digitally controllable implementation that preserves front-end gain and linearity, with a small penalty on receiver NF. A programmable 0.7-2.7-GHz front-end in 40-nm CMOS verifies the functionality. At 1.7 GHz, the front-end has a gain of 37 dB, a NF of 5.2 dB, and an out-of-band IIP3 of 1 dBm. Mikko Kaltiokallio (S'07-M'13) received the M.Sc. degree in electrical engineering from the Helsinki University of Technology, Espoo, Finland, in 2006. In 2014 he received the D.Sc. degree in the same field at Aalto University, Espoo, Finland. From 2005 to 2013, he was with the Electronic Circuit Design Laboratory, Helsinki University of Technology and later Aalto University. Since 2013, he has been with the Nokia Corp. working with front-end circuits. His research interests lie in the wideband high-linearity radio front-ends, mixed-signal RF and baseband design, and quadrature and LO buffering circuits. Kari Stadius (S'95-M'03) received the M.Sc., Lic. Tech., and D.Sc. degrees in electrical engineering from the Helsinki University of Technology, Helsinki, Finland, in 1994, 1997 He is currently working as a staff scientist at the Department of Micro-and Nanosciences, Aalto University School of Electrical Engineering, Finland. His research interests include CMOS RF circuits for communications with special emphasis on frequency synthesis, analog and mixed-mode circuit design, and new emerging RF technologies such as graphene. He has authored or coauthored over 70 refereed journal and conference papers in the areas of analog and RF circuit design.Kimmo Koli (M'95) was born in Karuna, Finland, in 1964. He received his M.Sc., Licentiate in Technology, and D.Sc. degrees in electrical on audio and sensor interfaces and wireless tranceivers. From 2008 to 2013, he joined STMicroelectronics (later ST-NXP Wireless and ST-Ericsson) and is currently with Ericsson, Turku, Finland, focusing on RF design blocks for wireless applications.Dr. Koli has authored or coauthored over 40 journal articles and conference papers and holds several patents. He has served for several years as a member of the technical program committee of IEEE International Solid-State Circuits

Next generation receivers, such as the direct ∆Σ receiver (DDSR), shift the boundary between analog and digital closer to the antenna by merging the functionalities of different sub-blocks. In the DDSR, the analog components are used to their maximum potential as each stage participates in amplification, blocker filtering, anti-aliasing, and quantization noise shaping simultaneously, resulting in a compact design. To overcome the increased design complexity, the implemented DDSRs rely on common practices in receiver and ∆Σ modulator design. In this paper, we will show that the common design practices for neither receivers nor ∆Σ modulators yield optimal performance for the DDSR, and propose a systematic design method for gmC based DDSRs. The method enables improved performance and straightforward design flow by combining the gain partitioning, noise considerations and loop-filter design. The developed method is demonstrated by designing a gmC based DDSR using a 28 nm FDSOI CMOS process. Simulations of the DDSR indicate stateof-the-art performance.

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