A Programmable 0.7–2.7 GHz Direct $\Delta \Sigma$ Receiver in 40 nm CMOS

Englund, Mikko; Ostman, Kim B.; Viitala, Olli; Kaltiokallio, Mikko; Stadius, Kari; Koli, Kimmo; Ryynänen, Jussi

doi:10.1109/jssc.2015.2397193

Cited by 36 publications

(24 citation statements)

References 21 publications

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“…A similar concept employing bandpass sampling at RF is discussed in [2], [49] though the concept was not implemented, and there are several drawbacks such as very stringent requirements on the ADC, the need of tunable RF filters, noise aliasing, and degradation of the SNR due to clock jitter. Another interesting development is the introduction of the direct DeltaSigma receiver [50]- [54]. This is also a direct RF to digital conversion approach, but combines the RF front-end with a feedback-type Delta-Sigma ADC [54].…”

Section: Sdr Receiversmentioning

confidence: 99%

See 1 more Smart Citation

Wireless Receiver Architectures Towards 5G: Where Are We?

Bronckers

Roc'h²,

Smolders³

2017

IEEE Circuits Syst. Mag.

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Section: Sdr Receiversmentioning

confidence: 99%

“…Another interesting development is the introduction of the direct DeltaSigma receiver [50]- [54]. This is also a direct RF to digital conversion approach, but combines the RF front-end with a feedback-type Delta-Sigma ADC [54]. Advantages include noise shaping at RF, full integration, and both tunable center frequency and bandwidth.…”

Section: Sdr Receiversmentioning

confidence: 99%

Wireless Receiver Architectures Towards 5G: Where Are We?

Bronckers

Roc'h²,

Smolders³

2017

IEEE Circuits Syst. Mag.

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“…Typically, a DDSR implements basic N-path filtering techniques for OB blocker rejection at the LNA output [1], [4]. However, there are two limitations with this approach.…”

Section: Blocker Rejection For a Ddsrmentioning

confidence: 99%

A wideband blocker-resilient direct ΔΣ receiver with selective input-impedance matching

Haq

Englund

Stadius

et al. 2017

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a wideband blocker-tolerant Direct ∆Σ receiver (DDSR). Blockers are attenuated through selective input impedance matching and optimized gain design. The created impedance profile provides low receiver input impedance at blocker frequencies, while at desired frequencies, the impedance is boosted to matched condition through an upconverted positive feedback from the DDSR output. Receiver is evaluated in a 28nm fully-depleted silicon-on-insulator CMOS process with total power consumption of 25mW at 1V supply voltage. The receiver is designed for configurable operation from 0.7-2.7GHz, a baseband bandwidth of 10MHz, demonstrates a maximum noise figure of 6.2dB, and achieves a peak SNDR of 53dB with an out-of-band 1dB input compression point of -11.5dBm at 100MHz offset.

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“…The noise figure of the system is limited by the clock jitter injected from the first feedback DAC. Compared to [28], [29], this system consumes much less power since it avoids the use of active resonators. By avoiding bulky passives, this design achieves the smallest reported area among all.…”

Section: Measurementmentioning

confidence: 99%

A Wideband 400 MHz-to-4 GHz Direct RF-to-Digital Multimode <formula formulatype="inline"><tex Notation="TeX">$\Delta\Sigma$</tex> </formula> Receiver

Wu¹,

Alon²,

Nikolić³

2014

IEEE J. Solid-State Circuits

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A wide-tuning-range low-power sigma-delta-based direct-RF-to-digital receiver architecture is implemented in 65 nm CMOS. A flat signal transfer function is chosen to support wide-frequency-range radios. A multilevel (two-bit) nonreturn-to-zero DAC improves jitter immunity to enable a high dynamic range, and, with a class-AB low-noise transconductance amplifier, guarantees a highly linear front end. For a 4 MHz signal, the peak SNDR of the receiver exceeds 68 dB and is better than 60 dB across the 400 MHz to 4 GHz carrier frequency range. By virtue of utilizing a negative feedback digitizer close to the antenna, an IIP3 of 10 dBm is achieved while dissipating only 40 mW from 1.1 V/1.5 V supply voltages.

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A Programmable 0.7–2.7 GHz Direct $\Delta \Sigma$ Receiver in 40 nm CMOS

Cited by 36 publications

References 21 publications

Wireless Receiver Architectures Towards 5G: Where Are We?

Wireless Receiver Architectures Towards 5G: Where Are We?

A wideband blocker-resilient direct ΔΣ receiver with selective input-impedance matching

A Wideband 400 MHz-to-4 GHz Direct RF-to-Digital Multimode <formula formulatype="inline"><tex Notation="TeX">$\Delta\Sigma$</tex> </formula> Receiver

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