We present a new way to passively implement permutation circuits, a concept of importance in bit-oriented or line-oriented designs, used in communications, cryptography, field-programmable gate arrays or next-generation pulsed neural networks. We argue that the proposed implementation is more reliable and efficient than previous designs when the number of permuted signals is at least 16. It uses complementary resistive gates, which are natural extensions of the concept of a complementary resistive switch. When Ir/TaO /Ta stack is used for switching, the devices show abrupt transitions among a discrete number of states resulting in a complex input-output characteristic. This deviates significantly from the fuzzy logic model of such gates previously proposed on the basis of theoretical models.
Pattern matching is a machine learning area that requires high-performance hardware. It has been hypothesized that massively parallel designs, which avoid von Neumann architecture, could provide a significant performance boost. Such designs can advantageously use memristive switches. This paper discusses a two-stage design that implements the induced ordered weighted average (IOWA) method for pattern matching. We outline the circuit structure and discuss how a functioning circuit can be achieved using metal oxide devices. We describe our simulations of memristive circuits and illustrate their performance on a vowel classification task.
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