Memristor-based pattern matching

Abstract

Pattern matching is a machine learning area that requires high-performance hardware. It has been hypothesized that massively parallel designs, which avoid von Neumann architecture, could provide a significant performance boost. Such designs can advantageously use memristive switches. This paper discusses a two-stage design that implements the induced ordered weighted average (IOWA) method for pattern matching. We outline the circuit structure and discuss how a functioning circuit can be achieved using metal oxide devices. We describe our simulations of memristive circuits and illustrate their performance on a vowel classification task.

Double-Forming Mechanism of TaOx-Based Resistive Memory Device and Its Synaptic Applications

“…As the CC increased, the width of the conducting filament also increased. Then, more electrons could move through the enlarged conducting path, resulting in a larger I LRS [ 44 , 57 ]. Consequently, I LRS increased, while I HRS remained unchanged.…”

“…These functions include the potentiation and depression of short- and long-term memory (STM and LTM, respectively), spike-rate-dependent plasticity, and spike-time-dependent plasticity (STDP). Controllable conductance and synaptic weight changes can be monitored using these methods [ 40 , 41 , 42 ], while complex tests (such as pattern recognition systems through handwritten Modified National Institute of Standards and Technology (MNIST) datasets) are often conducted to evaluate the use of memristors as artificial synapses [ 43 , 44 ].…”