Modern processor design tools integrate in their workflows generators for instruction set simulators (Iss) from architecture descriptions. Whilst these generated simulators are useful for design evaluation and software development, they suffer from poor performance. We present an ultra-fast Jitcompiled Iss generated from an ArchC description. We also introduce a novel partial evaluation optimisation, which further improves Jit compilation time and code quality. This results in a simulation rate of 510Mips for an Arm target across 45 Eembc and Spec benchmarks. On average, our Iss is 1.7 times faster than Simit-Arm, one of the fastest Iss generated from an architecture description.

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The increasing density of silicon processes, coupled with the development of ever more energy and space efficient embedded core designs, has led to multi-processor system-on-chip (MPSoC) designs becoming increasingly attractive for use in embedded systems. Unfortunately this increase in core count gives rise to an explosion in design space possibilities, especially when heterogeneous designs are considered. To address this problem, new techniques in simulation are required to increase the simulation performance of these systems, while maintaining the accuracy needed to make good design decisions, and to verify the performance characteristics for realtime systems. We present a new high-speed, near cycle-accurate simulator, addressing an important but neglected category of multicore systems: deeply-embedded cacheincoherent MPSoCs. We take advantage of the unique properties of these systems to relax synchronisation constraints and increase the parallelism of the simulation. In doing so we achieve performance not possible using previous simulation techniques, without compromising the accuracy of the results. Quantitative performance results are presented across a large range of simulated MPSoC designs, comprising 1-64 cores, on average we simulate at 5.7 MIPS, with simulation speeds reaching 377 MIPS in the best case. Comparing against FPGA implementations we demonstrate that the simulator manages this with an average timing error of only 2.1%. Applying some of B Christopher Thompson

Specialising Systems-on-Chip (SOCs) for a particular application is an effective way of increasing the performance achievable for a given level of energy consumption. In fact, silicon manufacture costs are low enough that small, custom, entirely digital designs, up to and including multi-core microprocessor designs, can be manufactured cheaply in short manufacturing runs. Non-recurring engineering (NRE) costs are still prohibitive due to the high level of experience required from the design engineer and the vast size of the design space. This is even true when only pre-verified Commercial Off-the-Shelf (COTS) Intellectual Property (IP) blocks are used in the SOC design. In this paper we present a novel machinelearning based method of generating an application-specific SOC design and configuration. This approach is fully automated and can generate near-optimal application-specific SOC designs within hours rather than weeks and, hence, reduce both NRE costs and time-to-market significantly. Our methodology profiles key application characteristics using simulation of a small number of test systems and machine-learning based prediction to find likely optimal system designs for a given target application. We demonstrate the effectiveness of our automated design methodology using 82 workload applications, generate SOC designs with up to 10 cores and 8 memory banks, and show that our classifier averages up to 92% of the optimal design performance across our applications.