Design Space Exploration of Hybrid Ultra Low Power Branch Predictors

Modern processors get great performance improvement by branch prediction, and two-level branch predictor is widely used because of its simple structure and high performance. But this kind of predictor has 3 limitations-Branch Alias, History Noise and Multi-way Access. In this paper, we propose an optimized mechanism named Record Branch Prediction, which records the PCs and GHR of previous executed branches in order to guide current branch prediction. We apply Record Branch Prediction on the traditional two-level branch predictors and implement Record-Gshare and Record2Bc-gskew. The results show that record predictors can get less prediction miss than original predictor without Record Branch Prediction. Besides, longer PC-Records and larger PHT capacity can reduce more prediction miss percentage for original predictor in general. As an example, Records-Gshare can reduce 7.6% prediction miss compared with Gshare and Records-2Bc-gskew can reduce 14.5% prediction miss compared with 2Bc-gskew on average when number of PC-Records entries is 20 and number of PHT entries is 4096.

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Design Space Exploration of Hybrid Ultra Low Power Branch Predictors

Cited by 5 publications

References 10 publications

Efficient architectural exploration of TAGE branch predictor for embedded processors

Efficient architectural exploration of TAGE branch predictor for embedded processors

LLM Based End-to-end Branch Predictor Optimization Generator

Record Branch Prediction: An Optimized Scheme for Two-level Branch Predictors

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