Abstract-IEEE 802.3an task force is now developing new Ethernet Standard-10GBase-T. Currently, most of the 10Gbps Ethernet is developed with fiber medium due to the fiber high bandwidth. However, the fiber and optical device cost are still too high to be popular. Therefore, our goal is to lower the 10GBase-T transceiver cost. We propose two new low cost 10GBase-T transceiver architectures. One is echo shortening. A Shortened Impulse Response Filter (SIRF) is used to shorten the echo impulse response to reduce the echo canceller cost. The other is joint shortening. The SIRF is used to jointly shorten impulse response of echo and NEXT. Moreover, compare with the conventional architecture, the cost saving of the proposed echo shortening and joint shortening architecture is 12% and 35% respectively.

Abstract. Echo canceller plays an important role in the full-duplex communication system. Conventional implementations of echo cancellers are often the adaptive transversal filter architectures due to the simplicity and robustness of stability and convergence. However, the conventional echo cancellers suffer from high cost problem especially when the response time of the echo is long. In this paper, a new cost-efficient architecture of echo cancellers, targeting on 10GBase-T Ethernet System, is presented. The proposed scheme inherits the concept of channel shortening which is widely employed in DSL systems. A shortened impulse response filter is implemented at the receiver to shorten the impulse response of the echo signal. Hence, the overall cost of echo cancellers can be reduced. We generalize the channel shortening architecture to a joint multi-channel shortening scheme. The joint multi-channel shortening architecture can be applied to multiple-input multiple-output wireline communication systems to further reduce both the cost of echo and near-end crosstalk (NEXT) cancellers. We apply the proposed scheme to 10GBase-T Ethernet system. The simulation results show that the proposed echo and NEXT cancellers can save up to 35% hardware cost compared to the conventional transversal implementations.