The influence of the dipole of an insulator surface on temporal changes in the source-drain current was investigated by using organic fieldeffect transistors with a surface-modified SiO 2 insulator. The source-drain current decreased drastically with respect to time when the dipoles of the insulator surface displaced slightly. In order to obtain highly stable organic transistors, it is thus necessary to remove the mobile dipoles from the insulator surface. #
We have investigated the effect of the surface roughness and surface wettability of silicon dioxide (SiO 2 ) on the threshold voltage shift caused by gate bias stressing in organic field-effect transistors (OFETs). We observed that the threshold voltage shift was extremely sensitive to changes in the small roughness of the SiO 2 surface; the shift increased with roughness. On the other hand, the threshold voltage shift was not significantly affected by the wettability of the SiO 2 surface. The large shift in OFETs with rough SiO 2 insulators can be attributed to lattice distortion in pentacene layers deposited on rough SiO 2 surfaces. We observed that long-time application of gate bias stress caused not only a threshold voltage shift but also a mobility decrease.
Epitaxial layers were grown on semi-insulating LEC GaAs substrates by the chloride CVD technique and depletion type MESFET's with a gate length of 0.5 am have been fabricated on these epitaxial layers. Correlation between the FET device performance and the substrate quality has been studied. It was found that the substrate quality largely affects the device performance. Dislocations of the substrate had no definite effect on the device performance, while the density of the precipitate-like microscopic defects revealed by AB solution had a decisive effect on the device performance and the uniformity. We have examined LEC GaAs substrates with various density of etch pits revealed by AB solution (AB-EPD) but with nearly the same order of dislocation density revealed by KOH etching. The AB-EPD ranged from less than 104 to 5 • 105 cm 2, while the average dislocation density was in the range of 1-3 z 10 4 cm -2. The standard deviation of the gm compression over 2 in. ~ wafers was very small in the case of low AB-EPD wafers, while it was very large in the case of high AB-EPD wafers. When the substrate with FETs was etched by AB solution after the device performance measurement, it became evident that FETs with several AB etch pits under the gate area exhibited lower performance. It was also found that the photoluminescence intensity and its distribution over the substrate corresponded with the etch pit pattern generated by the AB solution.
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