We consider modern design for manufacturing (DFM) as a manifestation of IC industry re-integration and intensive cost management dynamics. In that regard DFM is somewhat different from so-called design for yield (DFY) which essentially focuses on productivity (yield) management (that is not to say that DFM and DFY do not have significant overlaps and interactions). We clearly see the shaping of a new "full-chip DFM" infrastructure on the background of the "back to basics" designmanufacturing re-integration dynamics. In the presented work we are focusing on required DFM-efficiencies in a "foundry-fabless" link. Concepts of "virtual prototyping of manufacturing", "design process optimization", and "foundry-portable DFM" models are explored. Both senior management of the industry and leading design groups finally realize the need for a radical change of design styles. Some of the DFM super-goals are to isolate designers from process details and to make designs foundry portable. It requires qualification of designs at different foundries. In their turn, foundries specified and are implementing a set of DFM rules: "action-required", "recommended", and "guidelines" while asking designers to provide netlist and testing information. Also, we observe strong signs of innovation coming back to the mask industry. Powerful solutions are emerging and shaping up toward mask-centered IP as a business. While it seems that pure-play foundries have found their place for now in the "IDM+" model (supporting manufacturing capacity of IDMs) it is not obvious how sustainable the model is. Wafer as a production unit is not sufficient anymorefoundries are being asked by large customers to price products in terms of good die. It brings back the notion of the old ASIC business model where the foundry is responsible for dealing with both random and systematic yield issues for a given design. One scenario of future development would be that some of the leading foundries might eventually transform themselves into IDMs. Another visible trend: some of the manufacturing capacities started to diversify business by providing services for new emerging markets (for example, new energy and medicine applications). Finally it is very unclear what's going to happen to fabless players. We continue building on the "Think SPICE again!" methodology introduced last year and expanding on previous platforms' discussion. Model expression of DFM, most probably, will be supplied by the equipment suppliers and yield management community. Actual content for a design intent model will be provided by manufacturing. Much like SPICE it describes the behavior and not what the actual measurement in manufacturing is. When the model is available and populated, a design automation solution can be created that will allow a designer to extract, analyze, simulate, and optimize the circuit prior to handoff to manufacturing.
In this paper we review current design-to-silicon manufacturing challenges and complexities confronting the IC design and manufacturing worlds as the industry prepares for sub-1 OOnm technology node IC production and discuss a simplifying infrastructure and various principles for reducing and managing these complexities. Rapidly increasing overall complexity spanning all elements of the design-thru-silicon 'ecosystem' and entanglement of the intricacies of traditionally separable design and manufacturing process technical disciplines is increasingly evident in long-loop design-mask-FAB iterations portending a widening of the design-productivity gap and an impact on the costeffectiveness and productivity of the IC industry. Using the concept of 'technology overshoot' we conclude that the IC industry must broaden its development efforts and diversify investments to include those of building a robust and inherently simplifying interface infrastructure between design and manufacturing and to enable the efficiencies required of a maturing industry. We also explore the concept of modularity and how other mature industries have employed it to optimize efficiencies and investments and conclude that while the design and manufacturing worlds have practiced a number of fundamental concepts of modularity -the overall disaggregation of the industry as a whole as case in point --a consistent, well-planned architecture for managing the interface between the two worlds has not yet been employed; hindering the development and migration of much needed productivity and cost-effectiveness enhancements. We then discuss the impact of these factors on the industry in light of sub-wavelength era lithography resolution enhancement technologies (RET) and related manufacturing process and device physics issues, which increasingly impact the design flow. Recognizing that significant improvement to the design-silicon manufacturing interface is required, lastly we discuss a solution in the form of a new industry initiative called GDS-3. In our findings we acknowledge that the IC industry has already developed a solution, called OpenAccess, to a similar problem in the design space having to do with interoperability between design automation tools. We relate this work to the issues being faced between design and manufacturing and draw our final conclusion that the new design-to-manufacturing infrastructure (GDS-3) should be an augmentation of the design community's Open Access initiative.
Optical interconnects provide wide bandwidth, low loss, and high fanout as compared to those for traditional electrical interconnects. In the past years many high performance optoelectronic circuits have been demonstrated. However, most of them require complicated process and exotic devices. To make optical interconnects in real system and commercial use, circuits utilizing manufacturable, robust, and low-cost technology have to be realized. Ion implanted GaAs MESFETs provide great promise due to their simplicity in manufacturing and their high speed performance. The optical characteristics of GaAs materials also make this technology favorable in realizing low-cost, high-performance OEICs (Opto-Electronic Integrated Circuits).Based on the experience obtained in the successful implementation of the 10 GHz receivers [1] and motivated by the increasing demand for highly parallel optical interconnects, high-performance two-dimensional 4x4 and 8x8 smart-pixel arrays capable of detect, amplify, negate, and emit ( DANE) optical signals utilizing Vitesse's HGaAs-III 0.6 im E/D MESFET process have been developed. The main design goals are aggregated data rates of 16 and 64 Gb/s (at 1 Gb/s/channel for 4x4 and 8x8 arrays), power consumption of less than 100 mW/channel, and sensitivity of better than -20 dBm. To make the data transmission transparent, fully dc-coupled circuits are designed. Obstacles in array implementation are also overcame, by the novel design of the fully differential optical receivers. Approximately 5,000 and 20,000 active devices are integrated in the 4x4 and 8x8 arrays, respectively. The simulated results of the complete circuits show that the design goals of low power, high speed, high density, high sensitivity, high process and power supply tolerance are met.
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