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The CMOS technology is the mostly portable technology used in the designing of the circuits and in its fabrication. Designing of the circuits using CMOS technology requires the high power, high transistors count and low performance. The basic idea of the project is in order to reduce the count of transistors, time delay, and power consumption and to increase the performance of the circuits such as line decoders. The line decoder is a combinational circuits to which "n" no .of inputs are given as input and the output is 2^n based on the selected input and it requires 20 and more than 20 transistors to design any MxN decoders using CMOS technology .In order to configure the parameters and to make it more portable we are using different types of logic styles this usage of technologies more than one technologies on each circuit is a mixed logic styles .In this concept we observe the results as per required .The technologies we use in this is TGL/DVL. The suggested framework "Design about low Power, helter execution 2-4 What's more 4-16 blended rationale offering Decoders" is executed done 45nm engineering utilizing cadence virtuoso tool. The circuit schematic is designed and the circuits are simulated for functionality verification.

A novel idea of 8-Transistor (8T) static random access memory cell with enhanced information stability, sub threshold operation may be outlined. Those prescribed novel built single-ended for dynamic control 8 transistors static RAM (SRAM) cell enhances the static noise margin (SNM) to grater low energy supply. The suggested 8T takes less read and write power supply compared to 6T. Those suggested 8T need higher static noise margin than that from 6T. The portable microprocessor chips need ultralow energy consuming circuits on use battery to more drawn out span. The power utilization might be minimized utilizing non-conventional gadget structures, new circuit topologies, and upgrading the architecture. Although, voltage scaling require of the operation completed over sub threshold for low power consumption, and there will be an inconvenience from exponential decrease in execution. However, to sub threshold regime, that data stability of SRAM cell might a chance to be a amazing issue and worsens for those scaling from claming MOSFET ought to subnanometer engineering technology.