Abstract. An 8 bit segmented current steering DAC is presented for the compensation of mismatch of sensors with current output arranged in a large arrays. The DAC is implemented in a 1.8 V supply voltage 180 nm standard CMOS technology. Post layout simulations reveal that the design target concerning a sampling frequency of 2.6 MHz is exceeded, worst-case settling time equals 60.6 ns. The output current range is 0–10 μA, which translates into an LSB of 40 nA. Good linearity is achieved, INL < 0.5 LSB and DNL < 0.4 LSB, respectively. Static power consumption with the outputs operated at a voltage of 0.9 V is approximately 10 μW. Dynamic power, mainly consumed by switching activity of the digital circuit parts, amounts to 100 μW at 2.6 MHz operation frequency. Total area is 38.6 × 2933.0 μm2.

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A high spatiotemporal resolution, wireline operation-based, in-vivo neural recording system is presented. The proposed system allows selecting 64 channels from 512 recording sites. The neural signals from the 64 selected sites are amplified, filtered, and finally multiplexed in the time domain. The output signals of each multiplexer are buffered, converted to the current domain, and then transferred to off-chip units for further signal processing purposes. The proposed chip is simulated in a standard 180 nm CMOS process. Estimated input referred noise in the frequency band from 1 Hz to 10 kHz is 5.1 μV rms , and the total power consumption amounts to 3.3 mW at a supply voltage of 1.8 V.