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This paper presents modeling of a capacitive link for wireless data transfer to implantable biomedical microsystems. Based on the proposed model, voltage transfer ratio of the link is calculated, and its most important parameters are highlighted.To validate the suggested model, measurements are performed with 5 mm × 5mm plates, which have a layer of chicken breast with 3.5 mm thickness in between. Comparison between experimental results and model-based simulations shows that the model can be used for characterizing capacitive links.

This paper presents the design and implementation of a read-out chain for electrical impedance tomography (EIT) imaging. The EIT imaging approach can be incorporated to take spectral images of the tissue under study, offering an affordable, portable device for home health monitoring. A fast read-out channel covering a wide range of frequencies is a must for such applications. The proposed read-out channel comprising a programmable gain instrumentation amplifier, an analog-to-digital converter (ADC), and an ADC driver is designed and fabricated in a 0.18  m CMOS technology. The proposed read-out chain operates over the wide frequency range of 100 Hz to 10 MHz, with an average signal-to-noise ratio of more than 60 dB. The entire read-out channel consumes between 6.9 and 21.8 mW, depending on its frequency of operation.

In this paper, thorough analysis along with mathematical derivations of the matched filter for a voltmeter used in electrical impedance tomography systems are presented. The effect of the random noise in the system prior to the matched filter, generated by other components, are considered. Employing the presented equations allow system/circuit designers to find the maximum tolerable noise prior to the matched filter that leads to the target signal-to-noise ratio (SNR) of the voltmeter, without having to over-design internal components. A practical model was developed that should fall within 2 dB and 5 dB of the median SNR measurements of signal amplitude and phase, respectively. In order to validate our claims, simulation and experimental measurements have been performed with an analog-to-digital converter (ADC) followed by a digital matched filter, while the noise of the whole system was modeled as the input referred at the ADC input. The input signal was contaminated by a known value of additive white Gaussian noise (AWGN) noise, and the noise level was swept from 3% to 75% of the least significant bit (LSB) of the ADC. Differences between experimental and both simulated and analytical SNR values were less than 0.59 and 0.35 dB for RMS values ≥ 20% of an LSB and less than 1.45 and 2.58 dB for RMS values < 20% of an LSB for the amplitude and phase, respectively. Overall, this study provides a practical model for circuit designers in EIT, and a more accurate error analysis that was previously missing in EIT literature.

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