The major issue of RRAM is the uneven sneak path that limits the array size. For the first time record large One-Resistor (1R) RRAM array of 128x128 is realized, and the array cells at the worst case still have good Low-/High-Resistive State (LRS/HRS) current difference of 378 nA/16 nA, even without using the selector device. This array has extremely low read current of 9.7 μA due to both low-current RRAM device and circuit interaction, where a novel and simple scheme of a reference point by half selected cell and a differential amplifier (DA) were implemented in the circuit design.

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A novel content addressable memory (CAM) architecture with a simple but very effective precharge controller is presented. CAM is a hardware search mechanism that precharges all its match lines (MLs) during the precharge phase, and a search is performed during the evaluate phase. With unique words stored in a CAM, all the MLs except the one, which matches with the search word have to be discharged for every search cycle. The MLs that mismatch will anyway drain the charge during the evaluation phase, here, those mismatching MLs are predicted early during the precharge phase to terminate the full precharging of such lines. This promises CAM with reduced power as well as improved search speed.Index Terms-Content addressable memory (CAM), dynamic precharging, high-speed search, precharge controller, shortcircuit current. 1063-8210