In this paper, systematic implementation of current-mode RMS-to-DC converters based upon MOS translinear (MTL) principle, utilizing symmetric cascoded MTL cell (SCMC) is proposed. Theory of operation and mathematical analysis of both explicit (direct) and implicit (indirect) techniques for realization of SCMC-based RMS-to-DC converters are discussed. The SCMC includes a folded MTL loop and realizes an MTL equation. MTL principle utilizes the square law characteristics of saturated MOS transistors to realize square-root domain (SRD) functions. The SCMC is constructed by two connected cascoded current mirrors and has a compact, symmetric, and multi-purpose structure, with capability of implementing the circuits into the programmable and configurable structures. The proposed RMS-to-DC converters utilize the SCMC along with a configurable current mirror array. The required squaring and square-rooting functions are realized using the SCMC, after proper configuration of the current mirror array. The proposed circuits have been implemented using a reconfigurable architecture fabricated in a 0.5 μm CMOS technology.

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This paper describes the theory of operation, mathematical analysis, modeling and circuit design of the true piecewise approximation logarithmic amplifiers. These logarithmic amplifiers can be realized by the series linear limit and parallel summation methods. Both of these methods are discussed in this paper and their transfer functions are extracted. In addition, making use of the proposed formulas, a new mathematical approach is proposed for improving the characteristics of the parallel summation method. All of the presented methods are modeled in Simulink. Moreover, they are designed in a 0.13 lm CMOS technology and simulated by HSPICE. It is observed that analytical results comply with the simulation results. Considering the dynamic range, power, and area, the parallel summation method shows better performance than its series linear limit counterpart.