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The electrical performance of SiC-based microelectronic devices is strongly affected by the densities of interfacial traps introduced by the chemical and structural changes at the SiO2∕SiC interface during processing. We analyzed the structure and chemistry of this interface for the thermally grown SiO2∕4H-SiC heterostructure using high-resolution transmission electron microscopy (TEM), Z-contrast scanning TEM, and spatially resolved electron energy-loss spectroscopy. The analyses revealed the presence of distinct layers, several nanometers thick, on each side of the interface; additionally, partial amorphization of the top SiC surface was observed. These interfacial layers were attributed to the formation of a ternary Si–C–O phase during thermal oxidation.

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A method to form SiO2/SiC metal–oxide–semiconductor structures by oxidation of a thin polycrystalline silicon (polysilicon) layer deposited on SiC is demonstrated. The oxidation time used is sufficient to oxidize all the polysilicon while short enough at 1050 °C to insure insignificant oxidation of the underlying SiC. Since the oxidation of SiC is highly anisotropic, this method allows uniform oxide formation on a nonplanar SiC surface. The SiO2/SiC interface quality is comparable to that obtained with thermal oxidation.

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