As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single-and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

We demonstrate that modeling bulk traps and passivation/barrier interface traps in AlGaN/GaN HEMT is necessary to reproduce experimentally observed device behavior. Comparative modeling analysis of different leakage mechanisms in vertical p-n diode with a threading dislocation shows that variable range hopping is the dominant leakage mechanism there. The 3D quantum transport analysis of the impact of threading dislocations on electron mobility for sheet-like and nanowire-like GaN and Si MOSFET channels suggests considerable nanosheet variability and super-sensitive nanowire response. The analysis of voids in electrochemically induced pitting characterizes the impact of different pit types on different key metrics of transistor performance.

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