Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond

Feng, Peijie; Song, Seung-Chul; Nallapati, Giri; Zhu, John; Bao, Jerry; Moroz, Victor; Choi, Munkang; Lin, X. W.; Lü, Qiang; Colombeau, B.; Breil, N.; Chudzik, M.; Chidambaram, C.

doi:10.1109/led.2017.2769058

Cited by 38 publications

(19 citation statements)

References 4 publications

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“…Despite this, the NW FET still delivers the highest I ON /I OFF ratio. These NW FET characteristics, together with the possibility of stacking them vertically [3], [6], [7], suggest that the NW architecture makes an excellent candidate for low power applications. The NS FET has an I ON /I OFF ratio 37% smaller than the ratio of the NW FET and delivers a slightly better performance in the sub-threshold than that of the FinFET.…”

Section: Benchmarksmentioning

confidence: 99%

“…However, FinFETs will struggle to keep control of device electrostatics in future generations of complementary metaloxide-semiconductor (CMOS) technology [1]. The eventual changeover to different architectures like nanosheet (NS) [2]- [5] or nanowire (NW) FETs [6], [7], and/or to different channel materials like Ge or III-Vs [8]- [10] requires thorough ground work. Therefore, physically-based 3D simulations play an essential role to benchmark the most promising candidates.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, physically-based 3D simulations play an essential role to benchmark the most promising candidates. Although many works already compared FinFET and NW FET architectures [2], [10]- [12], there are fewer that include a predictive physically based comparison of FinFET, NS and NW FETs [6], [13], [14]. These works The associate editor coordinating the review of this manuscript and approving it for publication was Sun Junwei .…”

Section: Introductionmentioning

confidence: 99%

“…These works The associate editor coordinating the review of this manuscript and approving it for publication was Sun Junwei . use either drift-diffusion simulations [6] that cannot capture non-equilibrium carrier transport, or employ a quantum corrected Monte Carlo (MC) technique via a density gradient approach that requires calibration [7].…”

Section: Introductionmentioning

confidence: 99%

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Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

et al. 2020

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Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length (L G) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to L G of 16 nm offering a larger on-current (I ON) and slightly better sub-threshold characteristics. Below L G of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current (I OFF), and the largest I ON /I OFF ratio out of the three architectures. However, the NW FET suffers from early I ON saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.

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Section: Benchmarksmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

et al. 2020

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“…compared variously-shaped NSFET structures for maximum transistor performance [21]. In this NSFET structure paper, the authors proposed nanowires and nanosheets that possess hexagonal, rectangle, and oval shapes.…”

Section: Introductionmentioning

confidence: 99%

Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm

Song

2020

IEEE Access

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The GAAFET (gate-all-around FET) is expected to replace FinFETs in future nodes due to its excellent channel controllability. It is also expected to be an impressive device due to its horizontal or vertical transistor structures. Vertical GAAFETs (V-FETs) are expected to be a promising device compared to horizontal GAAFETs (H-FETs) due to their structure, which allows area reduction and significant parasitic reduction. Besides, V-FETs are positioned on top of each other and thus allow more significant size reductions. Therefore, this paper studies the overall potential of many-tier V-FETs by investigating the essential design factors from the layout perspective. First, we study the factors that should be considered for designing many-tier V-FETs. Second, we propose an interconnect structure that maximizes the advantages of many-tier V-FETs. Third, we compare 2-tier V-FET standard cells to one-tier V-FET cells and visualize the advantages that many-tier V-FET cells provide. Our study shows that 2-tier V-FET standard cells provide a-35.6% area reduction with a cost of +16.5% wirelength and +13.2% parasitic capacitance increase compared to 1-tier V-FET cells. Compared to H-FETs and FinFETs, our cells show-50.1% area reductions with-0.3% wirelength reductions and-18.9% parasitic capacitance reductions. We emphasize that the design freedom to place transistors on top of each other and proper interconnect structures lead to ultra-scale miniaturized standard cell designs. We note that the increase in wirelength and capacitance is due to the vertical size increases and detours that must exist in the designs. Thus, careful circuit design is required to obtain the maximum advantages from V-FETs.

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Growth of Nano‐Wire Field Effect Transistor in 21^stCentury

Sinha

2023

Nanodevices for Integrated Circuit Design

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Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond

Cited by 38 publications

References 4 publications

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm

Growth of Nano‐Wire Field Effect Transistor in 21^stCentury

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Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond

Cited by 38 publications

References 4 publications

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm

Growth of Nano‐Wire Field Effect Transistor in 21stCentury

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Growth of Nano‐Wire Field Effect Transistor in 21^stCentury