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Abstract. In this paper a common-gate LNA is presented, which is used in a low-power IEEE 802.15.4 receiver with severer requirements on the current consumption. The LNA is designed in a 0.25 μm CMOS technology and consumes only 831 μA. The LNA achieves a voltage gain of 12.89 dB, a NF of 4.86 dB, and an IIP3 of −6.0 dBm.

Frequency-hopping-spread-sprectrum wireless digital communication-systems impose stringent requirements on both phase noise and settling time of PLL based frequency synthesizers employed in receivers and transmitters. If a CA-fractional-N-Synthesizer is used either the reference frequency or the loop filter order must therefore he high. We theoretically investigate PLLs of higher order and find that the settling time of a sixth order PLL suitable for operation in a hluetoothtransceiver can be as low as 7ps in spite of a reference frequency of 16MHz.

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