Electron cyclotron emission (ECE) measurements on the tandem mirror GAMMA 10 are reported. The fifth-harmonic ECE in the thermal barrier region was measured in order to obtain the temporal and spatial evolution of hot electrons produced by electron cyclotron resonance heating for the formation of a thermal barrier potential well. The electron temperatures in the central and plug cells were determined using the second-harmonic ECE which was corrected for the hot-electron emission by considering a relativistic shift of resonance layers. The results, thus obtained, show strong evidence for the existence of a thermal barrier.

Silicon-on-insulator devices have problems with both performance and cost. We developed three advanced devices on bonded SOI produced using pulse-field-assisted bonding and selective polishing in an attempt to solve these problems. We tightly bonded highly implanted wafers, epitaxial wafers, and wafers covered with smoothed CVD oxide at temperatures below 1000~ We uniformly thinned bonded wafers by grinding, polishing, resistivity-sensitive etching, or selective polishing. We formed buried layers and buried electrodes by bonding and polishing techniques. Our high speed epitaxialbase transistor on 1-~m thick SOI has a cutoff frequency of 32 GHz. Our lateral bipolar transistor with a thin base on 0.15-~m thick SOI had a cutoff frequency of 4 GHz. A double-gate MOSFET on 60-nm thick SOI had a transconductance of more than twice that of a conventional SOI MOSFET. This paper discusses further advantages of bonded SOI techniques.Silicon-on-insulator (SOi) technology based on wafer bonding is an emerging technology for high-performance integrated circuits. The most useful SOI properties are a direct result of the ability to provide total electrical isolation. The quality of bonded SOI is similar to that of conventional bulk Si wafers, and bonded SOI usually can be used with conventional LSI processes. Material quality is no longer a barrier to widespread use of SOI. Many device types including DRAMs, CMOS SRAMs, ECL SRAMs, and high-voltage ICs have been fabricated on bonded SOI. 1-7 However, SOI devices on bonded SOI have not yet replaced bulk devices, except for high-voltage ICs and radiationhardened ICs. The SOI structure increases the speed of a circuit and reduces its power consumption because it reduces parasitic capacitance. However, these advantages are not realized without optimizing the circuit design. SOI devices have not replaced bulk devices because the advantages of the SOI structure do not outweigh the cost of changing circuit designs. High-voltage isolation and radiation-hardness are possible without any complicated design changes, and without compromises in speed and density. Also, these properties cannot be achieved easily with bulk ICs. As a result, only high-voltage telecommunications ICs and radiation-hardened ICs for military use are fabricated on SOI materials.There are two approaches to solving the problems with SOI technology. One is'to exploit the properties of the SOI structure to .their limit. The other is to save total cost by using SOI's inherent property of perfect and easy isolation. The device fabrication process using SOI should be less complex than the conventional process. Both approaches can use bonded SOI techniques, consisting of bonding and thinning, in conventional LSI processes.Bonding allows us to obtain single, crystalline materials on amorphous or polycrystalline materials and also can produce a buried layer of highly doped Si or electrodes as shown in Fig. i. An SOl wafer with a Ta silicide buried layer has been fabricated. 8 Thinning by polishing enables us to reduce the thi...

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