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A high-output-voltage micro-thermoelectric generator (µTEG) has been developed by fabricating thermocouples having a high aspect ratio (HAR) with a high integration density. They have been made by a novel and simple fabrication method, in which thermoelectric nanopowders are filled in a photosensitive glass mold by using aerosol deposition. It is followed by hot isostatic pressing to improve the thermoelectric property. This method has the possibility of increasing the aspect ratio of thermocouples drastically while increasing their toughness. We have fabricated thermocouples with an aspect ratio of 3.5 and a high integration density of 620 TCs cm–2. Their Seebeck coefficient and electrical resistivity are 290 µV K–1 and 1.5 mΩ cm, respectively, which make them as good as the thermocouples fabricated by hot pressing. By using the method, we have fabricated a µTEG chip having an area of 25 mm2 in which 56 thermocouples are arranged in an area of 9 mm2. The µTEG reaches a thermal resistance of 17.1 K W–1, output voltage efficiency of 0.16 V cm–2 K–1 and output power efficiency of 9.3 µW cm–2 K–2. These HAR thermocouples have an advantage for energy harvesting from a human body because they can result in a high temperature difference because of their high thermal resistance.

The uniformity of Josephson-junction (JJ) characteristics is crucial in wafer-scale superconducting quantum-bit (qubit) integration. To achieve the level of accuracy demanded the circuits, every detail of the fabrication process needs to be optimized. Here we reveal that the junction-resistance (RN) variations of Al/AlOx/Al JJs are affected by the metal deposition on the sidewall of the resist mask during shadow evaporation. The effect is reproduced in numerical simulation using a simple model taking into account the resist structure and the evaporation angle. To overcome the issue, we introduce a two-step shadow evaporation method to reduce the variation of RN. As a result, the coefficient of variations across a 3-inch wafer decreases from 6.7% to 4.5%, achieving 1.1% in a chip with an area of 10 mm × 10 mm. This method is promising for developing large-scale superconducting quantum computers.