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ABSTRACT:In this paper we are going to modify the Schmitt Trigger based SRAM cell using Negative Bias Temperature Instability (NBTI) for the purpose of more reduced power than the existing type of designs. As well as the new design which is combined of virtual grounding with read error reduction logic is compared with existing Schmitt trigger based SRAM technologies. Negative bias temperature instability (NBTI) is an important lifetime reliability problem in microprocessors. The Schmitt Trigger operation gives better read-stability as well as enhanced write-ability compared to the standard 6T bit cell. The aim of this project is to develop a circuit level technique that takes advantage of program behavior to reduce power consumption with no performance degradation. These simulations are implemented by the mentor graphics tool. I.