This letter demonstrates for the first time junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with ultrathin channels (2 nm). The subthreshold swing is 61 mV/decade and the ON/OFF current ratio is close to 10 8 because of the excellent gate controllability and ultrathin channel. The JL-GAA TFTs have a low drain-induced barrier lowering value of 6 mV/V, indicating greater suppression of the shortchannel effect than in JL-planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future system-on-panel and system-on-chip applications.Index Terms-Gate-all-around (GAA), junctionless (JL), thin-film transistor, ultrathin channel.

The high temperature dependence of junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with 2-nm-thick nanosheet channel is compared with that of JL planar TFTs. The variation of SS with temperature for JL GAA TFTs is close to the theoretical value (0.2 mV/dec/K), owing to the oxidation process to form a 2-nm-thick channel. The bandgap of 1.35 eV in JL GAA TFTs by fitting experimental data exhibits the quantum confinement effect, indicating greater suppression of Ioff than that in JL planar TFTs. The measured ∂Vth∂T of −1.34 mV/°C in JL GAA nanosheet TFTs has smaller temperature dependence than that of −5.01 mV/°C in JL planar TFTs.

The breakdown voltage (V BD) and breakdown mechanism of junctionless (JL) poly-Si thin film transistor (TFT) were compared to the conventional inversion-mode (IM) TFT using fabricated devices and 3D quantum-corrected hydrodynamic transport device simulation. The simulated results are correspondent with experimental ones. The analyses of electric field distributions in on-state show that the channel of JL devices can equally share the voltage like a resistor, because there are no junctions formed between channel and source/drain. The JL TFT shows excellent breakdown characteristics; the off-state V BD of 53.4 V is several times larger than V BD of 9.5 V in IM TFT with same device size. JL devices have large potential for high voltage power metal-oxide-semiconductor devices and circuit applications. V

This paper develops the n-channel and p-channel twin poly-Si fin field-effect transistor nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results demonstrate that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.6 V after 10 4 program and erase cycles, and after 10 years, the charge is 53.4% of its initial value. In the future, it can be applied in multilayer Si ICs in fully functional system-on-panel, active-matrix liquid-crystal display and 3-D stacked flash memory.Index Terms-Fin field-effect transistor (FinFET), flash memory, nanowires (NWs), nonvolatile memory (NVM), Ω-gate, 3-D, twin poly-Si.

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