Comprehensive Study of N-Channel and P-Channel Twin Poly-Si FinFET Nonvolatile Memory

Abstract

This paper develops the n-channel and p-channel twin poly-Si fin field-effect transistor nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results demonstrate that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.6 V after 10 4 program and erase cycles, and after 10 years, the charge is 53.4% of its initial value. In the future, it can be applied in multilayer Si ICs in fully functional system-on-panel, active-matrix liquid-crystal display and 3-D stacked flash memory.Index Terms-Fin field-effect transistor (FinFET), flash memory, nanowires (NWs), nonvolatile memory (NVM), Ω-gate, 3-D, twin poly-Si.

Charge Splitting In Situ Recorder (CSIR) for Real-Time Examination of Plasma Charging Effect in FinFET BEOL Processes

“…( 4 ). where Δ t is the duration of a plasma process [ 28 , 29 ] and C ANT is the total capacitance of the metal antenna, while A ANT is the charging area of an antenna. All the parameters used in the above calculations are summarized in Table 1 .…”

“…From previous reports [ 27 ], the peak levels of J e and J i are around − 0.15 and 0.35 mA/cm 2 , respectively. It has been found [ 28 , 29 ] that DC and AC/bi-directional gate stress on n-channel and p-channel FinFET results in different latent damage to the gate dielectric film. High voltage stresses with positive or negative DC bias and AC voltage with a switching frequency of 0.1 Hz are applied to conventional FinFET test samples, respectively.…”

Nanosheet-Compatible Complementary-Field Effect Transistor Logic Non-Volatile Memory Device

“…3,4 Recently, advanced process technologies such as FinFET or GAA nanosheet has been or will be adopted in mainstream CMOS. 5,6 Stacked nanosheet or the complementary FET (CFET) structure further improves density of logic NVM. In this study, we propose a novel CFET logic NVM with a fabrication process similar to our prior work on CFET for CMOS logic, 7 with the exception of the gate stack deposition process.…”

Artificial Defects in Si3N4Enhance Nonvolatile Memory Performance of Ultra-Thin Body Poly-Si Junctionless Field-Effect Transistors

“…Besides, the SONOS NVM not only has thinner tunnel oxide but also has good reliability. [12][13][14] In addition to a nitride layer for discrete storage, NVMs also have a nano crystal layer to improve retentionability. 15,16 Recent research 13 has used quantum dot (SOncOS) as deep trapping level, however, this work improved NN middle of interface defects as deep trapping level.…”