A basic process to fabricate Ru/rutile-Co-doped TiO 2 /Ru capacitors for 20 nm-technology generation of DRAMs and beyond was developed. The aim of this study is that the basic process provides foresights into EOT and leakage-current density requirements. We chose rutile-TiO 2 for the insulators to meet the requirement of relative permittivity and Ru to suppress leakage-current density. We found the as-deposited lower electrode of Ru crystallized into the rutile phase of TiO 2 with a relative permittivity of 109 due to the similarity of crystal structures and lattice constants between rutile-TiO 2 and rutile-RuO 2 , which was generated by oxidizing Ru with ambient oxygen. Furthermore, we confirmed that doping elements that had a small-ionic radius, such as Co, decreased leakage-current density. The dependence of the leakage current of Ru/Co-doped-TiO 2 /Ru capacitors on temperature and analysis of the band structure with X-ray photoelectron spectroscopy revealed that leakage-current density is determined by a balance between thermionic current and tunneling current through the Schottky barrier. Through calculations using a theoretical equation for these currents, the optimum percentage of Co was estimated to range from 0.3-0.6 % to meet requirement of leakage current for 20 nmDRAMs. The major requirements of memory-cell capacitors for dynamic random access memories (DRAMs) have been set for equivalent oxide thickness (EOT) and leakage-current density. Capacitors need capacitance of 25fF regardless of what generation they are to avoid reading error.1 Less EOT is necessary to maintain capacitance with shrunken memory-cell areas. Twenty-nanometer DRAMs require capacitors with EOTs of less than 0.45 nm.1 Therefore, the permittivity of insulators must be larger than 60 assuming their physical thickness is 7 nm.1 The leakage-current density, on the other hand, needs to be less than 10 −7 A/cm 2 regardless of the generation when 1 V is applied between electrodes.1 This requirement is to maintain a refresh time as long as 64 ms.Major candidates for insulators fulfilling target permittivity are rutile-TiO 2 and perovskite-SrTiO 3 .1 We face difficulties with deposition despite the potential large permittivity of SrTiO 3 . Atomic layer deposition (ALD) is necessary to fabricate DRAM capacitors due to their high conformity and ability to control thickness. Although their precursors needs vapor pressures of more than 100 Torr at deposition temperatures around 200-400• C, the vapor pressures of strontium such as Sr(thd) 2 are insufficient being less than 1 Torr.2 Therefore, it is still difficult to commercialize SrTiO 3 . However, there are precursors of TiO 2 such as titanium tetraisopropoxide (TTIP) that have vapor pressures higher than that of strontium. Thus, TiO 2 is the most likely material for the capacitor insulators of 20 nm-technology generation of DRAMs and beyond.Insulators with large permittivity tend to have smaller band gaps. 3 The candidate material for electrodes should have a large work function, which is kn...

We demonstrate 40-nm CMOS transistors for the 70-nm technology node. This transistor uses a high-k offset spacer (EOS: high-epsilon offset spacer) in achieving both a short-channel and high drivability along with SIN gate dielectrics with oxygenenriched interface (01-SIN) to suppress both the gate-leakage current and boron penetration. Consequently, N-MOSFET and P-MOSFET have high drive currents of 0.68 and 0.30 mA/pm, respectively, with I,,,, = I O nA/km, with an EOT value of 1.4nm.The record gate delay of 280 fs (3.6 THz), for an N-MOSFET with the gate length of I9 nm, has also been achieved. IntroductionThe requirements on the transistors for a CMOS technology that provides high-performance and low-power are high drive currents in a short-channel and a low-leakage current through -gate dielectric. However, lateral diffusion of the sourceldrain impurities makes it difficult to obtain a gate length shorter than 50 nm, even with spike annealing. Although offset spacers are applied in most transistors for the 100-nm technology node to achieve gate lengths in the 50-70 nm range [ I ] , it is not possible to apply thicker offset spacers to obtain sub-50-nm gate lengths. This is because the low impurity concentration just outside the gate raises the external resistance (Rex,) [2]. We propose an EOS structure which reduces the value of R,,, by creating an inversion layer outside the gate. On the other hand, gate-leakage current (I,) is at a non-negligible level for an

The reduction of reverse leakage currents was attempted to fabricate 4H-SiC diodes with large current capacity for high voltage applications. Firstly diodes with Schottky metal of titanium (Ti) with active areas of 2.6 mm2 were fabricated to investigate the mechanisms of reverse leakage currents. The reverse current of a Ti Schottky barrier diode (SBD) is well explained by the tunneling current through the Schottky barrier. Then, the effects of Schottky barrier height and electric field on the reverse currents were investigated. The high Schottky barrier metal of nickel (Ni) effectively reduced the reverse leakage current to 2 x 10-3 times that of the Ti SBD. The suppression of the electric field at the Schottky junction by applying a junction barrier Schottky (JBS) structure reduced the reverse leakage current to 10-2 times that of the Ni SBD. JBS structure with high Schottky barrier metal of Ni was applied to fabricate large chip-size SiC diodes and we achieved 30 A- and 75 A-diodes with low leakage current and high breakdown voltage of 4 kV.

A Feasible fabrication process of Ru/rutile-Co-doped TiO2/Ru capacitor for 40-nm DRAM and beyond is developed. As-deposited Ru lower electrode is found out to crystallize Co-doped TiO2 overlayer into rutile having relative permittivity beyond 90 owing to lattice matching. Furthermore, we predicted doping of element having small ionic radius, such as Co, increase Schottky barrier, leading to decrease in leakage current. Temperature dependence of leakage current of RIR-Co-doped-TiO2 capacitor and band structure analysis with X-ray photoelectron spectroscopy shows that leakage current is determined by balancing between thermionic current and tunneling current through Schottky barrier. By doping of Co, the thermionic current decreases, whereas the tunneling current increases. With calculation using theoretical dependence of amount of doped element on leakage current, optimum percentage of Co is estimated as 0.3-0.6 % to achieve a sufficiently low leakage-current. This technology opens possibility to utilize 40-nm DRAM and beyond.

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