On-chip interconnects are becoming a major power consumer in scaled VLSI design. Consequently, bus power reduction has become effective for total power reduction on chip multiprocessors and system-on-a-chip requiring long interconnects as buses. In this paper, we advocate the use of bus serialization to reduce bus power consumption. Bus serialization decreases the number of wires and increases the pitch between the wires. The wider pitch decreases the coupling capacitances of the wires, and consequently reduces bus power consumption. Evaluation results indicate that our technique can reduce bus power consumption by 30% in the 45 nm technology process.

In a clustered microarchitecture design, the execution core which has large RAMs, large CAMs and all connected result bypass loops is partitioned into smaller execution cores that are called clusters. Clustered microarchitecture can allow a scalable core design because intra-cluster operation remains fast regardless of entire execution width of the core.But localization of critical memory transfers (store-loadconsumer) is still a problem. In this work, we propose a technique named "Distributed Speculative Memory Forwarding (DSMF)" that localizes critical memory transfers into a cluster. DSMF learns memory dependences at retire stage, steers dependent pair of the store and the consumer to the same cluster, transfers data locally in the cluster. We show that the IPC improvement of 15% was obtained by this localization on the baseline clustered microarchitecture.