Bus Serialization for Reducing Power Consumption

Abstract

On-chip interconnects are becoming a major power consumer in scaled VLSI design. Consequently, bus power reduction has become effective for total power reduction on chip multiprocessors and system-on-a-chip requiring long interconnects as buses. In this paper, we advocate the use of bus serialization to reduce bus power consumption. Bus serialization decreases the number of wires and increases the pitch between the wires. The wider pitch decreases the coupling capacitances of the wires, and consequently reduces bus power consumption. Evaluation results indicate that our technique can reduce bus power consumption by 30% in the 45 nm technology process.

On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

“…Memory bus power minimization techniques can be categorized as bus serialization [2][3][4], encoding [5][6][7][8], and compression techniques [9][10][11][12][13][14]. Non-cache-based encoding techniques reduce power by reordering the bus signals.…”

“…Suresh et al [7] presented a data bus transmit protocol called the power protocol to reduce the dynamic power dissipation of off-chip data buses. Hatta et al [2] proposed the concept of bus serialization-widening (SW) to reduce wire capacitance; their work focused on the power minimization of the on-chip cache address and data bus. Li et al [15] proposed reordering the bus transactions to reduce the off-chip bus power.…”

“…The total capacitance is the sum of the load capacitance and coupling capacitance and it can be expressed as = + 2 [2,16,[21][22][23]. The equation of the power consumption calculation of the conventional bus line will be…”

“…The signal transition switching activity [2,22] is given by = { 0 if data transition from 0 → 0 or 1 → * 1 if data transition from 0 → 1.…”

“…The coupling switching activity [2,22] depends on the transitions activity between two adjacent bus lines as follows: …”