No abstract

Graphene has been widely heralded over the last decade as one of the most promising nanomaterials for integrated, miniaturized applications spanning from nanoelectronics, interconnections, thermal management, sensing, to optoelectronics. Graphene grown on silicon carbide is currently the most likely candidate to fulfill this promise. As a matter of fact, the capability to synthesize high-quality graphene over large areas using processes and substrates compatible as much as possible with the well-established semiconductor manufacturing technologies is one crucial requirement. We review here, the enormous scientific and technological advances achieved in terms of epitaxial growth of graphene from thermal decomposition of bulk silicon carbide and the fine control of the graphene electronic properties through intercalation. Finally, we discuss perspectives on epitaxial graphene growth from silicon carbide on silicon, a particularly challenging area that could result in maximum benefit for the integration of graphene with silicon technologies.

wafer-scale, with good crystallinity and with contamination levels compatible with large-scale back-end-of-line (BEOL) integration. At present, chemical vapor deposition (CVD) on catalytic copper (Cu) substrates is widely recognized as the most promising route to obtain scalable monolayer graphene for electronic and optoelectronic applications. [1][2][3][4] However, significant hurdles are limiting the actual integration of CVD graphene grown on Cu for most applications. In the first instance, the unavoidable transfer process over wafer-scale is rather cumbersome and introduces contamination, unintentional doping, and mechanical stress, [5][6][7] which adversely impact the physical integrity and electrical performance [8] of the graphene layer. The significant challenge involved in carrying out this seemingly straightforward task is reflected by the vast literature on large-scale transfer processes. Second, metallic contamination levels in transferred CVD graphene grown on Cu are typically well-above the specifications requested for BEOL integration. [6] Clearly, asThe adoption of graphene in electronics, optoelectronics, and photonics is hindered by the difficulty in obtaining high-quality material on technologically relevant substrates, over wafer-scale sizes, and with metal contamination levels compatible with industrial requirements. To date, the direct growth of graphene on insulating substrates has proved to be challenging, usually requiring metal-catalysts or yielding defective graphene. In this work, a metal-free approach implemented in commercially available reactors to obtain high-quality monolayer graphene on c-plane sapphire substrates via chemical vapor deposition is demonstrated. Low energy electron diffraction, low energy electron microscopy, and scanning tunneling microscopy measurements identify the Al-rich reconstruction9° of sapphire to be crucial for obtaining epitaxial graphene. Raman spectroscopy and electrical transport measurements reveal high-quality graphene with mobilities consistently above 2000 cm 2 V −1 s −1 . The process is scaled up to 4 and 6 in. wafers sizes and metal contamination levels are retrieved to be within the limits for back-end-ofline integration. The growth process introduced here establishes a method for the synthesis of wafer-scale graphene films on a technologically viable basis.

The growth of graphene on SiC/Si substrates is an appealing alternative to the growth on bulk SiC for cost reduction and to better integrate the material with Si based electronic devices. In this paper, we present a thorough in-situ study of the growth of epitaxial graphene on 3C SiC (111)/Si (111) substrates via high temperature annealing (ranging from 1125˚C to 1375˚C) in ultra high vacuum (UHV). The quality and number of graphene layers have been investigated by using X-ray Photoelectron Spectroscopy (XPS), while the surface characterization have been studied by Scanning Tunnelling Microscopy (STM). Ex-situ Raman spectroscopy measurements confirm our findings, which demonstrate the exponential dependence of the number of graphene layer from the annealing temperature.