SUMMARYJob Management Systems (JMSs) efficiently schedule and monitor jobs in parallel and distributed computing environments. Therefore, they are critical for improving the utilization of expensive resources in high-performance computing systems and centers, and an important component of Grid software infrastructure. With many JMSs available commercially and in the public domain, it is difficult to choose an optimum JMS for a given computing environment. In this paper, we present the results of the first empirical study of JMSs reported in the literature. Four commonly used systems, LSF, PBS Pro, Sun Grid Engine/CODINE, and Condor were considered. The study has revealed important strengths and weaknesses of these JMSs under different operational conditions. For example, LSF was shown to exhibit excellent throughput for a wide range of job types and submission rates. Alternatively, CODINE appeared to outperform other systems in terms of the average turn-around time for small jobs, and PBS appeared to excel in terms of turn-around time for relatively larger jobs.

In this paper, we overview general hardware architecture and a programming model of SRC-6E TM reconfigurable computers, and compare the performance of the SRC-6E machine vs. Intel® Pentium IV TM . SRC-6E execution time measurements have been performed using three different approaches. In the first approach, the entire end-to-end execution time is taken into account. In the second approach, the configuration time of FPGAs have been omitted. In the third approach both configuration and data transfer overheads have been omitted. All measurements have been done for different numbers of data blocks. The results show that the SRC-6E can outperform a general-purpose microprocessor for computationally intensive algorithms by a factor of over 1500. However, overhead due to configuration and data transfer must be properly dealt with by the application or the system's run-time environment to achieve the full throughput potential. Some techniques are suggested to minimize the influence of the configuration time and maximize the overall end-to-end system performance 1 . 1: IntroductionThe SRC-6E Reconfigurable Computing Environment is one of the first general-purpose reconfigurable computing machines combining the flexibility of traditional microprocessors with the power of Field Programmable Gate Arrays (FPGAs). In this environment, computations can be divided into those executed using microprocessor instructions, and those executed in reconfigurable hardware. The programming model is aimed at separating programmers from the details of the hardware description, and allowing them to focus on an implemented function. This approach allows the use of software programmers and mathematicians in the development of the code, and substantially decreases the time to the solution.1 This work was partially supported by Department of Defense through the LUCITE contract no. MDA904-98-CA0810000.In this paper we investigate the possible speed-up that can be obtained using the SRC-6E Reconfigurable Computing Environment vs. a traditional PC based on the Pentium 4 microprocessor. Our benchmarks consist of the high-throughput implementations of Triple DES and DES Breaker algorithms in both environments. Triple DES, is one of the three standardized secret-key ciphers recommended for use in the U.S. government, and is widely used worldwide in multiple commercial applications. DES Breaker is a technique for breaking an old encryption standard, DES, based upon an exhaustive key search algorithm, i.e., testing all possible encryption keys one by one. 2: SRC-6E General Purpose Reconfigurable Computer Hardware architectureSRC-6E is a hybrid-architecture platform, which consists of two double-processor boards and one MultiAdaptive Processor (MAP TM ) module (see Figure 1). The MAP module consists of two MAP processors, each including two user programmable Xilinx® Virtex II XC2V TM 6000 FPGA devices. This way, the SRC-6E system achieves a 1:1 microprocessor to FPGA ratio. Processor boards are connected to the MAP processors through the so-call...

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Reconfigurable Computers can leverage the synergism between conventional processors and FPGAs to provide both hardware functionalities and general-purpose computers flexibility. In a large class of applications on these platforms, the data-transfer overheads can be comparable or even greater than the useful computations which can degrade the overall performance. In this paper, we perform a theoretical and experimental study of this specific limitation. The mathematical formulation of the problem has been experimentally verified on the state-of-the-art reconfigurable platform, SRC-6E. We demonstrate and quantify the possible solution to this problem that exploits the system-level parallelism within reconfigurable machines.