Deformation potential (D ac ), which determines the strength of electron-phonon scattering, is one of the most important physical parameters of Si. A longstanding unresolved question in D ac is that D ac for MOSFETs is considered to be much greater than D ac for bulk Si. In this work, we have demonstrated for the first time that D ac increases sharply at MOS interfaces within several-nm range. Because of the enhanced D ac at MOS interface, D ac for nanoscale SOI channel is expected to be increased owing to the high surface-to-volume ratio, which is verified by electron mobility calculations in extremely-thin SOI (ETSOI) MOSFETs and experimental stress-induced mobility enhancement in nanoscale SOI.

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The self-heating effects (SHEs) of bulk and silicon-on-insulator (SOI) fin-type field-effect transistors (FinFETs) and their impacts on circuit performance have been investigated on the basis of a realistic thermal conductivity of silicon. The heat dissipation via interconnect wires and interface thermal resistance in the high-κ gate stack were incorporated in simulations. It is shown that the depth of the shallow trench isolation (STI) of bulk FinFETs cannot be decreased to less than 100 nm owing to the increase in off-state leakage current. We observed that the thermal resistance R th of SOI FinFETs greatly decreases upon thinning the buried oxide (BOX) layer. When the BOX thickness t BOX is less than 50 nm, the R th of SOI FinFETs is smaller than that of bulk FinFETs with an STI thickness of 100 nm, indicating a lower operation temperature of the thin-BOX SOI FinFETs than that of bulk FinFETs. The lower operation temperature of the 5-nm BOX SOI FinFET was confirmed under a practical bias condition for analog operations. In fin width, W fin, versus R th characteristics, a strong W fin dependence of R th was observed only in the bulk FinFETs, implying that fluctuations in W fin result in the variability of the operation temperature of the bulk FinFETs. Analog performance has been analyzed by calculating the cutoff frequency f T and the maximum oscillation frequency f max. We demonstrated that both f T and f max can be maximized in SOI FinFETs by optimizing t BOX with regard to electrical and thermal properties. Better analog performance, and hence the optimization of t BOX, are indispensable for the device design of a FinFET-based system-on-a-chip (SoC) platform.

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