This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum (DS-SS) communication system. The proposed architectural approach to reducing the power consumption focuses on the reception registers and the correlation-calculating unit (CCU), which dissipate the majority of the power in a DMF The main features are asynchronous latch clock generation for the reception registers, parallelism of the correlation calculation operations and bit manipulation for chipcorrelation operations. A DMF is designed in compliance with the W-CDMA specifications incorporating the proposed techniques, and its properties are evaluated by computer simulations at the gate level using 0.18-jJm CMOS standard cell array technology. The results of the simulations show a power consumption of 9.3 mW (@15.6MHz, 1.6V), which is only about 30% of the power consumption of conventional DMFs. MF (AMF) [12]. An AMF is more power-efficient for shorter, faster MFs and a DMF is more power-efficient when the filters are longer or slower [13]. Recent advances in CMOS technology are making it possible to design a DMF for practical use. For application to code acquisition or tracking in DS-SS systems such as W-CDMA or post W-CDMA, in which relatively long reference codes are potentially present, a DMF is preferred for the design flexibility that it allows as well as for power efficiency.The use of a DMF for code acquisition in DS-SS systems might consume a good half of the total power in the base-band processing circuit if no low-power measures are included. It is desirable that the power consumption in the DMF is kept below 10 mW in order to maintain a practical active standby time. In [5] and [7], the main focus is on low-power techniques, including the architecture, circuitry and layout necessary to implement a low-power DMF. In this paper, we propose an architecture dedicated to the low-power design of a DMF applicable to W -CDMA.We consider reducing the switching probability in both the reception registers and the correlation-calculating block. The main points of the proposal are the use of asynchronous latch clock generation for the reception registers, parallelism of the correlation calculation operations and bit manipulation for chip-correlation operations in the CCU.

This paper presents an OFDM transceiver for wireless LAN systems and its baseband transceiver architecture. TYPICAL PARAMETERS IN PACKET-ORIENTED OFDM SYSTEMS. We study the optimum parameters about DFT size, guard K DFT size interval, symbol duration, and number of subcarriers in an 80-Fb Bandwidth (Hz) MHz bandwidth by extending the IEEE802.11a standard. The T Guard interval (s) proposed transceiver has a maximum 300-Mbps transmit rate Tg DFT window length (s) and achieves 600 Mbps by use of a 4x2 MIMO system. We Tf OFDM frame length (s) have designed the SISO-OFDM transceiver in a 0.25-,um CMOS N8 Number of data subcarriers technology. The transceiver consumes about 800 mW at 2.5-V Nb Coded bits per subcarrier power supply and 80-MHz clock frequency. For verification, the R Coding ratearchitecture has been implemented to a FPGA prototype. We describe the parameters of our proposal and the TGn Sync optional proposal by comparison.

A Digital Matched Filter (DMF) is an essential device for Direct-Sequence Spread-Spectrum (DS-SS) communication systems. Reducing the power consumption of a DMF is especially critical for battery-powered terminals. The reception registers and the correlation-calculating unit dissipate the majority of the power in a DMF. In this paper we discuss this problem and propose a lowpower architectural approach to a DMF. The total switching activity factor and the switched capacitance are reduced. As a result of power analysis at the gate level, the implementation of the proposed architecture in a standard 0.18ym CMOS technology achieved a reduction in the power consumption of more than 70%.

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A Digital Matched Filter (DMF) is an essential device for Direct-Sequence Spread-Spectrum (DS-SS) communication systems. Reducing the power consumption of a DMF is especially critical for battery-powered terminals. The reception registers and the correlation-calculating unit dissipate the majority of the power in a DMF. In this paper we discuss this problem and propose a lowpower architectural approach to a DMF. The total switching activity factor and the switched capacitance are reduced. As a result of power analysis at the gate level, the implementation of the proposed architecture in a standard 0.18-µm CMOS technology achieved a reduction in the power consumption of more than 70 %.