To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% per generation, device designers have been forced to relax the device subthreshold leakage continuously from one to several nA/lm for the 250-nm node to hundreds of nA/lm for the 65-nm node. Consequently, passive power density is now a significant portion of the power budget of a high-speed microprocessor. In this paper we discuss device and material options to improve device performance when conventional scaling is power-constrained. These options can be separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior. In the first category fall advanced dielectrics and multi-gate devices. The second category comprises mobility-enhancing measures through stress and substrate material alternatives. The third category focuses mainly on scaling of SOI body thickness to reduce capacitance. We do not provide details of the fabrication of these different device options or the manufacturing challenges that must be met. Rather, we discuss the fundamental scaling issues related to the various device options. We conclude with a brief discussion of the ultimate FET close to the fundamental silicon device limit. Gate length (nm) ERROR: See p. 361A.

We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6nm and SO1 channels as thin as 4nm are presented. For the frst time, we report ring oscillators with 26nm gate lengths and ultra-thm Si channels.10.6.2 268-IEDM

Band-to-band tunneling was studied in ion-implanted P/N junction diodes with profiles representative of present and future silicon complementary metal–oxide–silicon (CMOS) field effect transistors. Measurements were done over a wide range of temperatures and implant parameters. Profile parameters were derived from analysis of capacitance versus voltage characteristics, and compared to secondary-ion mass spectroscopy analysis. When the tunneling current was plotted against the effective tunneling distance (tunneling distance corrected for band curvature) a quasi-universal exponential reduction of tunneling current versus, tunneling distance was found with an attenuation length of 0.38 nm, corresponding to a tunneling effective mass of 0.29 times the free electron mass (m0), and an extrapolated tunneling current at zero tunnel distance of 5.3×107 A/cm2 at 300 K. These results are directly applicable for predicting drain to substrate currents in CMOS transistors on bulk silicon, and body currents in CMOS transistors in silicon-on-insulator.

No abstract

Since power dissipation is becoming a dominant limitation on the continued improvement of CMOS technology, technologists must understand the best way to design transistors in the presence of power constraints. The primary objective is to obtain as much performance as possible for a fixed amount of power, and it is chip performance, not device performance, that matters. In order to investigate this regime, we have captured in simplified models the basic elements for determining chip performance, including intrinsic transistor characteristics, circuit delay, tolerance issues, basic microprocessor composition, and power dissipation and heat removal considerations. These models have been assembled in a processor-level technology-optimization program to study the characteristics of optimal technology across many generations of CMOS. The results that are presented elucidate the limits of future CMOS technology improvements, the optimal energy consumption conditions, and the relative benefits of various proposed technology enhancements, including high-k gate insulators, metal gates, highmobility semiconductors, improved heat removal, and the use of multiple layers of circuitry.