Extreme scaling with ultra-thin Si channel MOSFETs

Doris, B.; Ieong, M.; Kanarsky, T.; Zhang, Ying; Roy, R.; Dokumaci, O.; Ren, Zhibin; Jamin, F.; Shi, L.; Natzle, W.; Huang, Hsing Hua; Mezzapelle, J.; Mocuta, A.; Womack, S.; Gribelyuk, M.; Jones, E.C.; Miller, R.J.; Wong, Hiu Yung; Haensch, Wilfried

doi:10.1109/iedm.2002.1175829

Cited by 126 publications

(89 citation statements)

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“…High-performance UTB device technologies have also been reported by other research groups [37], [43], [44] ( Table 1). In [37], gate lengths down to 6 nm were achieved by the introduction of an ultrathin gate dielectric and strong halo implant, which can further improve the control of short-channel effects.…”

Section: Ultrathin Body Single-gate Mosfetmentioning

confidence: 66%

“…In [37], gate lengths down to 6 nm were achieved by the introduction of an ultrathin gate dielectric and strong halo implant, which can further improve the control of short-channel effects.…”

Section: Ultrathin Body Single-gate Mosfetmentioning

confidence: 99%

“…9 shows the measured subthreshold characteristics for 300-nm gate length UTB PMOSFETs 15 nm using pure and nitrogen-implanted Mo gate [27]. The measured Mo-gated PMOS threshold voltage In the UTB device structure, the body thickness should be as thin as possible for ultimate scalability; however, the series resistance of the source and drain regions could limit transistor drive currents [35]- [37]. By using selective deposition, a raised source/drain structure can be created to reduce the parasitic resistance.…”

Section: Ultrathin Body Single-gate Mosfetmentioning

confidence: 99%

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Extremely scaled silicon nano-CMOS devices

Chang¹,

Choi

Ha³

et al. 2003

Proc. IEEE

219

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Section: Ultrathin Body Single-gate Mosfetmentioning

confidence: 66%

Section: Ultrathin Body Single-gate Mosfetmentioning

confidence: 99%

Section: Ultrathin Body Single-gate Mosfetmentioning

confidence: 99%

See 1 more Smart Citation

Extremely scaled silicon nano-CMOS devices

Chang¹,

Choi

Ha³

et al. 2003

Proc. IEEE

219

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“…The only major challenge is the alignment of gate pads between every pair of dots with a high degree of reliability. Recent demonstration of field effect transistors with 6 nm gate length [59] shows that lithography is advancing to the level where such challenges can be met.…”

Section: Current Experimental Status Of Sslmentioning

confidence: 99%

Information Processing with Electron Spins

Bandyopadhyay

2012

ISRN Materials Science

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Information processors process information in a variety of ways. The human brain processes information through a highly interconnected system of neurons and synapses, while a digital computer processes information by having a binary switch toggle on and off in response to a stream of binary bits. The "switch" is the most primitive unit of the modern computer. The better it is (faster, more energy efficient, more reliable, etc.), the more advanced is the computer hardware. Energy efficiency, however, is more important than any other attribute, not so much because energy is costly, but because too much energy dissipation prevents increasing the density of switches on a chip that is necessary to make the chip increasingly more powerful. Reducing dissipation entails radically new and often revolutionary approaches for implementing the switch. One such approach is to encode digital bit information in the spin polarization of a single electron (or ensemble of electrons) and then using two mutually antiparallel polarizations to represent the binary bits 0 and 1. Switching between the bits can be accomplished by simply flipping the polarizations of the spins, which takes very little energy. Such switches are extremely energy efficient if designed properly, but they are somewhat slower than traditional transistor-based switches and can be more error prone. This paper discusses the pros and cons of spin-based switches and introduces the reader to the most recent advancements in information processing predicated on encoding information in electron spin polarization.

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“…A number of different designs are under consideration for sub 10 nm gate length transistors. The use of very thin silicon on insulator substrates has already lead to working transistors with 6 nm gate lengths [20,21]. Another means of increasing drive current is to increase the area of the gate electrode through either multiple gates or wrap-around gates.…”

Section: Trend: Modeling Will Be An Increasingly Important Means Of Cmentioning

confidence: 99%

Metrology (including Materials Characterization) for Nanoelectronics

Diebold¹

2005

AIP Conference Proceedings

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Extreme scaling with ultra-thin Si channel MOSFETs

Cited by 126 publications

References 1 publication

Extremely scaled silicon nano-CMOS devices

Extremely scaled silicon nano-CMOS devices

Information Processing with Electron Spins

Metrology (including Materials Characterization) for Nanoelectronics

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