This work concerns the development of a radiation hardness assurance methodology specially devoted to CMOS, JI'ET and bipolar transistors used in high total dose level environments. On the basis of recent studies, high tempe:rature, high dose rate irradiations were performed. We propose a test procedure which combines high temperature irradiations and isochronal anneals for the qualification. 0-7803-4071-X/98/$'10.00 0 1998 IEEE.
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