A hybrid delta-sigma/pipelined modulator is presented in this paper. The proposed modulator takes advantage of the high resolution and distributed pipelined quantization, and combines it with the noise shaping property of a delta-sigma modulator. As a result, gain, swing, and slew requirements of the integrators are significantly reduced. The modulator also makes use of the latency in the pipelined quantization to enhance noise shaping. These advantages lead to less power dissipation, increased stability, and higher resolution. The prototype chip is implemented in a 0.18 m CMOS process. With an 80 MHz clock, and an oversampling ratio of 8 (5 MHz bandwidth), the measured dynamic range and SNDR of this prototype IC are 79 dB and 75.4 dB.

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A new comparator based MDAC is presented. This structure utilizes nonlinear charge transfer and time shifted CDS techniques to improve the performance of the comparator based MDAC. Simulation results show that the proposed MDAC can be utilized in pipeline ADCs to enhance accuracy and speed.

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Abstract-A new delta-sigma Analog-to-Digital Converter (ADC) is presented in this paper. A two-step pipeline ADC is used as the quantizer of this delta-sigma modulator to reduce the quantization noise at the output of the modulator. The proposed structure relaxes the output swing and gain requirements of the integrators. In addition, the front-end DAC of the proposed modulator is simplified. Simulation results verify the effectiveness of the proposed architecture.