Time-Shifted CDS Enhancement of Comparator-Based MDAC for Pipelined ADC Applications

Rajaee, O.; Maghari, Nima; Moon, Un-Ku

doi:10.1109/icecs.2007.4510967

Cited by 6 publications

(5 citation statements)

References 2 publications

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“…Circuit techniques such as correlated double sampling can be implemented to reduce the overshoot error for CBSC biquads, whereas the exponential settling requirement in opamp-based SC circuits is difficult to circumvent [14], [15].…”

Section: Discussionmentioning

confidence: 99%

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Analysis of Errors in a Comparator-Based Switched-Capacitor Biquad Filter

White

Luschas

Krishnan

2009

IEEE Trans. Circuits Syst. II

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Comparator-based switched-capacitor (CBSC) techniques have become popular in reducing power consumption and increasing the speed of data converters. This brief investigates the use of CBSC techniques for implementing a biquad filter. A CBSC implementation of a low-pass biquad is proposed, and the sources of error are analyzed. It is shown that implementing the lossy integrator as the last stage produces a lower offset voltage. The sensitivity of the biquad ω 0 and Q to the CBSC overshoot error is shown to be similar to that of the finite operational amplifier gain error in a switched-capacitor filter. Simulation results confirm the presented theory.Index Terms-Biquad, comparator-based switched capacitor (CBSC), switched-capacitor (SC) filter.

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Section: Discussionmentioning

confidence: 99%

“…shows the simulated frequency response of the CBSC biquad for different values of t D /RC, as well as the continuous-time second-order transfer function defined by (8),(9),(14),(15), and…”

mentioning

confidence: 99%

Analysis of Errors in a Comparator-Based Switched-Capacitor Biquad Filter

White

Luschas

Krishnan

2009

IEEE Trans. Circuits Syst. II

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“…3 illustrates the proposed CBSC MDAC with TSCDS. This technique is similar to [5]. To diminish the count of switch in the comparator plus input during the charge transfer phase, the stored overshoot voltage is used to adjust the threshold voltage of comparator minus input.…”

Section: Tscds For Cbsc Circuitmentioning

confidence: 99%

A 9-bit 50 MS/s CBSC pipelined ADC using time-shifted correlated double sampling

Hsiao

Chao

Hsu

et al. 2011

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Comparator-based switched-capacitor (CBSC) circuit provides a solution for insufficient impedance of the transistor in the advanced process, but the accuracy suffers from the overshoot error caused by comparator delay. In this paper, a time-shifted correlated double sampling (TSCDS) scheme for CBSC circuit is proposed to alleviate the overshoot error as well as mitigating double loading. Moreover, we propose an overshoot correction technique to further suppress the overshoot after employing TSCDS. Speed bottleneck in the conventional CBSC circuit is limited by the fine discharging phase. With the proposed TSCDS and the overshoot correction, the CBSC circuit exploits the coarse charging and removes the fine discharging phase to achieve a 9-bit 50 MS/s pipelined ADC. Simulation results demonstrate a 54.3-dB SNDR is achieved with 3.65-mW power consumption in 90-nm CMOS process and 1.2-V supply.

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“…This shows that the input integrator is very important for oversampling delta-sigma modulators [2][3][4][5][6][7][8][9][10][11][12]. The CBSC integrator shown in Fig.…”

Section: Input Cbsc Integrator For Delta-sigma Modulatormentioning

confidence: 99%

“…The Comparator-Based Switched-Capacitor Circuits (CBSC) is an appropriate method to design circuits by today technology [1][2][3][4][5][6][7][8][9][10][11][12][13]. With OPAMP based circuits, the accuracy of the circuit is very dependent of the open loop gain of the OPAMPs [14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%