A 9-bit 50 MS/s CBSC pipelined ADC using time-shifted correlated double sampling

Abstract

Comparator-based switched-capacitor (CBSC) circuit provides a solution for insufficient impedance of the transistor in the advanced process, but the accuracy suffers from the overshoot error caused by comparator delay. In this paper, a time-shifted correlated double sampling (TSCDS) scheme for CBSC circuit is proposed to alleviate the overshoot error as well as mitigating double loading. Moreover, we propose an overshoot correction technique to further suppress the overshoot after employing TSCDS. Speed bottleneck in the conventional CBSC circuit is limited by the fine discharging phase. With the proposed TSCDS and the overshoot correction, the CBSC circuit exploits the coarse charging and removes the fine discharging phase to achieve a 9-bit 50 MS/s pipelined ADC. Simulation results demonstrate a 54.3-dB SNDR is achieved with 3.65-mW power consumption in 90-nm CMOS process and 1.2-V supply.