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A Structured Application-specific Integrated Circuit (SASIC) is a programmable fabric in which a small set of masks are customized for a particular application, serving to reduce the associated non-recurring engineering cost (NRE). In this paper we describe the implementation of a SASIC logic cell which is programmable via a single metal layer. A SASIC fabric prototype is fabricated and all implemented functions are verified on silicon. Experimental measurement verifies correct operation of our SASIC with a clock frequency of over 250MHz. Keywords-application specific integrated circuits; digital integrated circuits; field programmable gate arrays I. INTORDUCTIONApplication-specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs) are the two main technologies for implementing digital designs. ASICs have advantages in terms of area, power, and speed but an expensive set of masks must be created for every design. In contrast, the mask costs are amortized over all of the users in FPGAs at the expense of lower performance and higher power consumption. A SASIC is a programmable fabric offering a middle ground between the two in which a small set of masks is customized for a particular application, serving to reduce the associated NRE and turn-around time [11].In the UMC 0.13µm single-poly 8-metal CMOS process, a full mask set for a standard cell ASIC consists of 40 layers [18] but a SASIC needs only one-tenth of those layers for configuration. Compared to FPGAs, SASICs offer improved density and speed as logic configuration and programmable routing can be implemented directly using metal and vias instead of static ram and multiplexers. As a result, SASICs are a compelling choice for medium volume production [3]. There have been previously reported SASIC designs but many are commercial and details of their implementations have not been published [6][9][11][12][13][16]. Of the reported ones in academia, such as [4][5][7][8][10], most have not been fabricated and proven on silicon.In this paper, we describe a SASIC library in which a single type of logic block can be configured for both combinatorial logic functions and sequential functions. In contrast to the work of [14] and [15] having fixed metal routing structure, our design adopts standard-cell ASIC approaches so there is no predefined routing fabric and clock tree. This allows critical path optimization and multiple clock domain support. The design flow is also highly compatible with industrial-level commercial tools.The key contributions of this paper are:• A SASIC logic cell design programmable using a metal layer. • A SASIC fabric that makes use of the logic cell library. • A fabricated SASIC prototype for verification.In the remainder of this paper, we present and evaluate our design. In Section II we describe the structure and the configuration framework of our SASIC library. In Section III, we present the evaluation fabric and circuits. Section IV shows the performance evaluation. Finally, Section V gives conclusions. II. SASIC LIBRARY...

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