Structured ASIC: Methodology and comparison

Ho, Sam M.H.; Yuen, Sze-Kit; Poon, Hiu Ching; Chau, Thomas; Ai, Yanqing; Leong, Philip H. W.; Choy, Oliver C.S.; Pun, Kong-Pang

doi:10.1109/fpt.2010.5681422

Cited by 4 publications

(2 citation statements)

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“…FPGA design consumes larger static power than the ASIC design due to excessive leakage currents [21][22][23], which is due to more number of transistors per logic. Other components, which are responsible for larger power consumption, are circuits used to provide flexibility to FPGA, number of configuration bits, lookup-tables (LUTs), and presence of large number of programmable switches.…”

Section: Power Consumption In Sram-based Fpgasmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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The design of low-power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAMbased FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA.

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