We report the development of high performance InP high electron mobility transistors (HEMTs) supported with three interconnect metal layers suitable for advanced RF and mixed signal integrated circuits. Depletion and enhancement mode devices with 35 nm gate-lengths are available with fT / fmax of 536/307 GHz and fT / fmax of 550/346 GHz, respectively. The process shows excellent device uniformity, yield, and reliability. The technology was used to demonstrate broadband feedbacklinearized amplifiers with 20dB S 21 gain and an OIP3 of 37 dBm at 2 GHz operation, where P DC is only 313mW.

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We present a compact, 3-stage millimeter-wave monolithic integrated circuit (MMIC) amplifier with an operating frequency of 206-294GHz, formed by common-source configured 35nm Lg InP mHEMTs and a multi-layer thin-film microstrip (TFM) wiring environment. The amplifier S21 mid-band gain gain is 11-16dB, 3dB bandwidth at 294GHz, and 82.5mW Pdc. This is the first reported InP HEMT MMIC operating in G-,H-band employing thin-film microstrip. Because the TFM ground-plane shields the signal interconnects from the substrate, well behaved device (0. and amplifier (210-320GHz) measurements are presented from an unthinned, 25mil substrate. The total size of this 3-stage amplifier is only 0.77mm x 0.40mm.

A report is presented on 100 nm and 200 nm InAs PHEMTs on an InP substrate with a record f T performance. This result was obtained by reducing a parasitic delay associated with the extrinsic gate capacitances of the device, as well as by using an InAs sub-channel to improve carrier transport properties. In particular, a 100 nm InAs PHEMT exhibits excellent performance, such as g m,max ¼ 2 S/mm, f T ¼ 421 GHz and f max ¼ 620 GHz at V DS ¼ 0.7 V. The device also shows a well-balanced f T and f max in excess of 400 GHz, even at V DS ¼ 0.5 V. In addition, the device gains about 70 % improvement in f T as L g shrinks down from 200 to 100 nm. The results obtained in this work should make this technology of great interest to a multiplicity of applications and guide a realistic path in trying to achieve a 1 THz f T from III-V HEMTs in the future.Introduction: Over the past three decades, gate length (L g ) scaling has been the key technology driver in III-V HEMTs with the InGaAs/ InAlAs material system to demonstrate record high frequency performance, as assessed by current-gain cutoff frequency (f T ) and maximum oscillation frequency (f max ). Recent reports on record high frequency characteristics of InGaAs/InAlAs HEMTs have been published with L g ¼ 30 -40 nm [1-3]. These improvements in RF performance have also arisen partly from the use of an indium-rich InAs sub-channel that increases the average electron velocity under the gate and improves charge control behaviour in the channel.Despite the record values that have been obtained for sub-100 nm InP HEMTs, clearly there exists scope for further improvement. In fact, the literature on record values of f T in III-V HEMTs reveals that only a 57 % improvement in f T is obtained by reducing L g from 130 nm [4] to 30 nm [1], indicating that the device suffers from an increased influence of parasitic delay terms and poor short-channel effects [5]. Without any doubt, the full benefit of L g scaling requires the minimisation of the delay associated with parasitic resistances and extrinsic gate capacitances, as L g scales down deeply. In particular, the parasitic delay due to the extrinsic fringing gate capacitance (C g,ext ) plays a more important role as L g shrinks, because the intrinsic gate capacitance (C gi ) scales down linearly with L g . In this Letter, we report that a systematic reduction of the parasitic delay associated with the extrinsic gate capacitance leads to an excellent high frequency performance in InAs PHEMTs on an InP substrate. In particular, our device exhibits a record f T ¼ 421 GHz at L g ¼ 100 nm and f T ¼ 250 GHz at L g ¼ 200 nm.

In this paper, we report the successful integration of high performance 0.5μm heterojunction bipolar transistors (HBTs) and 35nm high electron mobility transistors (HEMT) on an indium phosphide (InP) substrate. Both transistors demonstrate power gain cutoff frequencies (f max ) in excess of 300GHz, a ~2x improvement over previously reported results from integrated InP devices. The device epitaxy is grown in a single growth with the HEMT beneath the HBT sub-collector. Optimization of the device epitaxy and the HEMT lithography processes allow for HEMT-to-HBT separation of <10μm.The monolithic integration of field-effect and bipolar devices increases the functionality of RF and mixed-signal IC technologies. Recently, FETs have been added to GaAs HBT processes for the cellular handset amplifier markets [1]. These technologies are optimized for low cost and moderate performance. Transistor cutoff frequencies are <100GHz. InP HEMTs and HBTs are the fastest transistors demonstrated to date, with cutoff frequencies above 500 GHz. The InP HEMT is suitable for low-noise applications and low-loss switches. The InP HBT is suitable for higher breakdown circuits and supports high transistor counts by virtue of mV-level threshold uniformity. The intimate integration of both devices provides both benefits for circuit designers, opening the door to compact, low power, high performance transceivers.Previous attempts to integrate InP HBTs and HEMTs on the same substrate were undertaken almost a decade ago. Configurations included etch-and-regrowth processes, stacked epi-layers, and HEMT/HBT stacks with optical detectors [2][3][4]. These attempts came with shortfalls. Etch-and-regrowth approaches are costly and make intimate placement of the two types of devices difficult. Stacked approaches suffered from large topology associated with early generation HEMT and HBT epitaxy (close to 2μm each). In these previous demonstrations, HEMT gate lengths were >100nm, HBT emitter dimensions were >1μm, and RF cutoff frequencies were less than 160GHz. In this work, the integration of highly scaled 35nm gate length HEMTs and 0.5μm emitter width HBTs is enabled by aggressive vertical scaling of the device epitaxy.The stacked HEMT/HBT layers were grown by molecular beam epitaxy (MBE) on 4" InP substrates. The HEMT structure features a pseudomorphic In 0.7 Ga 0.3 As channel. Details of the device epitaxy can be found in [5]. Carrier density and mobility of 3.0×10 12 cm -2 and 10,000 cm 2 /V-s was measured from Hall calibration samples. The HBT epitaxial design is identical to TSC's baseline structure [6]. Features of the HBT epitaxy include a thin InP emitter (<40nm), a 40 nm compositionally graded InGaAs base layer, a 150nm thick InP collector, and chirped superlattice grading of the baseemitter and base-collector heterojunctions. We note that HBT epitaxy growth begins immediately on the HEMT cap layers with no intermediate buffer layer, and that the total epitaxial layer thickness is <1μm.Device processing begins with HBT fabrication using TSC's ...