Background: The major birch pollen allergen Bet v 1 (or Bet v 1a) is one of the main causes of seasonal type I allergies. Various environmental factors such as light, temperature and air pollution may influence the activity of the Bet v 1a gene. The creation of a model system to evaluate the role of environmental factors affecting the Bet v 1a gene expression would be highly desirable. We suggest the use of transgenic tobacco plants carrying a Bet v 1a promoter-reporter gene fusion as such a system. Methods: The promoter of the Bet v 1a gene was isolated with the use of the Universal Genome Walker kit (BD Biosciences Clontech, USA). Web Software was used to search for putative cis-regulatory elements within the promoter. Transgenic tobacco plants harboring the promoter-β-glucuronidase (GUS) reporter gene fusion were obtained via Agrobacterium tumefaciens-mediated transformation. Promoter activity was examined with histochemical and quantitative assays. Results: Structural analysis predicted elements responsible for pollen-specific, light-, stress- and hormone-mediated induction within the Bet v 1a promoter. The evaluation of GUS activity in transgenic tobacco plants showed that the Bet v 1a promoter is pollen-specific. Moreover, the Bet v 1a promoter is considered to be the strongest isolated pollen-specific promoter reported to date. It was shown that temperature and abscisic acid positively regulate the activity of the Bet v 1a promoter during pollen development, providing evidence for environment-dependent regulation of the Bet v 1a gene. Conclusions: A model system to study the effect of environmental factors on the expression of the Bet v 1a gene encoding the major birch allergen in pollen was generated. Additionally, we suggest that this system could be used to search for factors that inhibit the activity of the gene in pollen in order to reduce the potential allergenicity of birch trees.

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Multibit feedback, being one way of lowering 16 modulators power consumption, has a major obstacle: the number of components in the internal analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Nevertheless, the number of comparators in the ADC can be significantly reduced depending on the order of noise-shaping and the oversampling ratio. In this paper, we propose an auto-ranging algorithm with a mechanism to keep the structure stable that emulates more quantization levels than that allowed by the number of comparators. As the recourse to segmented DACs allows lowering the complexity of the mismatch shaping encoder, the auto-ranging ADC brings the benefits of multibit feedback without the usual increase in size and power consumption. The internal number of bits in 16 16 16 modulators is no more restricted by the difficulty of building the flash ADC with a low voltage supply.Index Terms-Adaptive algorithm, auto-ranging, delta-sigma (16), dynamic element matching (DEM), low voltage, multibit.

Trends in wireless circuits toward more sophisticated digital signal processing increase demand for low-power low-supply highresolution analog-to-digital converters. This Σ∆ modulator converts the GSM IF spectrum using a low intermediate frequency (IF). The choice of the A/D resolution is crucial for accurate digital channel selectivity and at the same time to meet the requirements of the EDGE standard. The single-bit 2-2-cascaded modulator architecture is shown in Figure 3.2.1. Compared with highorder single-loop architectures, cascaded structures are more demanding in terms of component matching and amplifier gain. However, stability is ensured by cascading of low-order stages. The modulator uses a 13MHz clock to achieve an ultimate dynamic range of 84dB over 189kHz bandwidth (BW). Resonance is employed in the second stage to spread the zeros of the noise transfer function over the bandwidth and thus enhance noiseshaping efficiency. Although creating resonance requires a small capacitor, behavioral simulations show that the modulator SNR is not sensitive to the accuracy of the resonance path coefficient. The ideal modulator achieves 98dB peak SNR for a -1.3dB input and it remains >90dB for the worst-case of capacitor mismatch. The modulator SNR is ultimately limited by thermal noise. Power consumption is directly related to the total circuit capacitance. So accurate estimation of the thermal noise is essential to determine the value of the sampling and feedback capacitors in the first integrator [1]. Capacitors in the following stages are scaled down to minimize the power consumption.Coefficients maximizing the integrator output voltage swing are necessary for a low-power design [2]. However, high voltage swings require amplifiers capable of maintaining DC gain over the full output voltage swing. Behavioral simulations show that a minimum DC gain of 65dB in the three first OTAs is mandatory for the ideal SNR=98dB, while for the last stage a DC gain as low as 30dB is sufficient. Considering three main factors: gain, supply voltage and noise, a Miller-compensated amplifier is used in the three first stages (Figure 3.2.2-a) and a current-mirror amplifier is preferred for the last stage (Figure 3.2.2-b). The advantages of a Miller-amplifier are: high-gain, high-output swing and low input-referred noise. Joint system and circuitlevel design specifies the speed requirements of each OTA. The minimum unity-gain-bandwidth (UGBW) and slew-rate for the OTAs ensure the required settling accuracy. In two-stage amplifiers, in addition to the sensing common-mode (CM) feedback circuit, an extra CM-amplifier is needed [2]. Using a current-mirror with 20/3 ratio in the CM-amplifier allows high CM-UGBW and low bias current. However, care is taken to keep the associated extra pole as high as possible to preserve the CM-path phase margin. Regarding the stability and power considerations, the compensation capacitor of each Miller OTA is equal to the sampling capacitor of the next integrator. The compensation series resistors are nMO...