GaAs-based MOSFETs have been a subject of study for several decades. Both GaAs-based native oxides and deposited insulating layers have been attempted as the gate dielectrics. Limited progress has been achieved. Only recently promising results have been demonstrated using an in-situ Ga203(Gd203) gate dielectric grown by MBE[l]. In this paper, we demonstrate for the first time GaAs-based MOSFETs with excellent performance using an A1203 gate dielectric grown by atomic layer deposition (ALD). ALD (which is a variant of CVD) is a very robust, highly manufacturable process[2].The GaAs MOSFET devices, as shown in Fig. 1, employed A1203 gate dielectric of thicknesses ranging from 80 to 500 A, and a 700A Si-doped (4x17 ~m -~) GaAs layer as the channel, and gate lengths down to 0.65 pm.The A1203 films were deposited by ALD in an ASM hlsar2O0OTM module after channel layer formation. The abrupt interface is illustrated by the HRTEM image in Fig. 2. All wafers were transferred in air before and after ALD growth, with no requirement for UHV conditions, demonstrating a significant advance towards manufacturability.Operation between a gate bias (V,) of +4V to -6SV results in a very low gate leakage current of -10-4A/cm2 (Fig. 3), with the inset showing the scalability of breakdown voltage with A1203 physical thickness. Wellbehaved I-V characteristics of a GaAs MOSFET with negligible hysteresis are shown in Fig. 4. Figure 5 shows the drain current as a function of gate bias in different sweep directions. The maximum transconductance g, is -100 m S / m at this gate length, and increases to -130 m S / m at L, = 0.65 p. The large transconductances with negligible hysteresis indicate that interface trap densities are sufficiently low. In order to understand better the interface properties, we studied the spectrum of the straps by measuring g, vs. frequency (Fig.6) and performing simulations (Fig.7). The analysis gives an upper limit for the interface trap density (DJ of 5x10'' to 10'2/cm2-eV at such A1203/GaAs structures. Very encouraging RF performance is also presented,in Fig. 8, wherefT andf,, are 14 and 25 GHz at L, = 0.65 pm. The device performance of g, vs. V, -at' positive bias is further improved by using a composite channel of thin strained InozG%.*As/GaAs layers. In Fig. 9, a significant increase of IDS at positive gate bias demonstrates that this device is operated in a strong accumulation regime. We ascribe this improvement to a higher-quality interface ofA120$InGaAs and higher mobility of electrons in the InGaAs channel.We demonstrate the use of ALD A1203 gate dielectrics for GaAs-based MOSFETs, with excellent transistor performance. These results suggest new opportunities for supplying alternative, including high-lc, gate dielectrics and passivation layers grown by ALD for III-V semiconductor devices. I -[l] M. Hong et al., Encyclop.
