This paper presents the design of an asynchronous version of the TR4101 embedded microprocessor core developed by LSI Logic Inc. The asynchronous processor, called ARISC, was designed using the same CAD tools and the same standard c ell library that was used to implement the TR4101.The paper reports on the design methodology, the architecture, the implementation, and the performance of the ARISC. This includes a comparison with the TR4101, and a detailed b r eakdown of the power consumption in the ARISC.ARISC is our rst attempt at an asynchronous implementation and a number of simplifying decisions were made up front. Throughout the entire design we use four-phase handshaking in combination with a normally opaque latch controller. All logic is implemented using static logic standard c ells. Despite this the ARISC performs surprisingly well: In 0.35 m CMOS performance is 74-123 MIPS depending on the instruction mix, and at 74 MIPS the power e ciency is 635 MIPS Watt.

The paper describes a design framework, Architect, being developed for synthesizing application-specific array architectures from behavioral specifications to Register-Transfer (RT) descriptions, which can be identified as a number of cooperating tasks: signal transformations, hardware mapping expressed as, in general, nonlinear spatial mapping and scheduling function with hardware constraints, memory management and controller synthesis.We present novel extensions to existing formal (i.e. ILP) and heuristics methods for multiplexing and clustering allowing constrained hardware allocation. Also a novel approach for optimizing on-chip memory is presented.

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