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The effect of dielectric constant and barrier height on the WKB modeled tunnel currents of MOS capacitors with effective oxide thickness of 2.0 nm is described. We first present the WKB numerical model used to determine the tunneling currents. The results of this model indicate that alternative dielectrics with higher dielectric constants show lower tunneling currents than SiO 2 at expected operating voltages. The results of SiO 2 /alternative dielectric stacks indicate currents which are asymmetric with electric field direction. The tunneling current of these stacks at low biases decreases with decreasing SiO 2 thickness. Furthermore, as the dielectric constant of an insulator increased, the effect of a thin layer of SiO 2 on the current characteristics of the dielectric stack increases. Semiconductor Research Corporation (SRC Contract 132).

Electrical properties of epitaxial CeO2 thin films on silicon (111) substrates grown in ultrahigh vacuum were studied, varying growth conditions and ex situ thermal treatments. Characterization using reflection high-energy electron diffraction and high resolution transmission electron microscopy reveal that while the ceramic layers have a good single-crystal structure, a dual amorphous layer of CeOx and SiO2 forms at the CeO2/Si interface. This structure has undesirable electrical properties, however, utilizing a post-anneal in dry oxygen, the α-CeOx layer was removed and the SiO2 amorphous layer was made thicker. This newly developed structure benefits from the SiO2/Si interface, having Dit=6×1011 cm−2, and Qf=5×1011 cm−2. The structure exhibits a high capacitance due to the large dielectric constant of CeO2, has electrical properties comparable with those of other reported gate insulators on Si, and has an epitaxial oxide lattice matched to Si.

Recent trends in the semiconductor industry indicate the need to explore alternatives to batch-wafer manufacturing. One proposed alternative is a micro-factory based on cluster tools. This paper presents an analysis of the effect of redundant chamhers and chamber revisitation process sequences on the throughput in an individual cluster tool. Theoretical models which quantify the time required to process a lot of wafers in a cluster tool are developed for these situations. The differences between scheduling algorithms which use the load-lock as a queue and those that do not are also explored. Finally, the models developed in the work are integrated into a model which bounds the minimum theoretical turn-around-time which can be achieved in a cluster based fab.

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