Accurate statistical models of FET devices are needed for yield-oriented MMIC design. In particular, currently used linear statistical models are not adequate in applications where bias point variations have a strong impact on overall yield. The paper describes a nonlinear statistical model of MESFET and HEMT devices in which statistical parameters are considered as Gaussian multivariate random variables. An automatic procedure is developed to achieve extraction of the statistical model of a FET device from a database of DC Ids and S-parameter measurements, and it is checked on a GaAs HEMT monolithic process. A statistical model has been extracted for Philips PML-D02AH GaAs HEMT devices and accurate evaluation of the S-parameters covariance matrix has been made. Statistical pair-wise tests on mean values, standard deviations and correlation coefficients show that the proposed methodology has the capability of reproducing statistical population distributions

-A circuit topology that provides large bandwidth single-ended to differential conversion is presented. The proposed cell is based on a differential pair where feedback on common mode signal provides about 6 dB conversion gain increase, together with attenuation of common mode signal. Small-signal characterisation is presented, based on a block decomposition of the cell. Measurements on a SiGe test IC show more than 5 dB of gain improvement with respect to a simple differential pair.

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Power analysis attacks exploit the existence of "side channels" in implementations of cryptographic algorithms to extract secret data. The scientific literature reports consolidated methods - such as Differential Power Analysis (DPA) and Simple Power Analysis (SPA) - for extracting a secret cryptographic key through the sensing of the hardware power consumption. We propose a novel dynamic and differential CMOS logic style as a countermeasure against power attacks on cryptographic devices. The proposed logic family exploits the idea of using signals with 3 possible states and operates with power consumption ideally independent on both the logic values and the sequence of data. We have designed a set of logic gates, flip flops and a simple S-BOX, and compared the S-BOX against previously published secure logic styles in terms of transistor count, power consumption and correlation between data and power dissipation. © 2008 IEEE