The first high-NA EUVL scanner will have an 0.55 NA and will use anamorphic magnification. Therefore, the standard 10×13 cm lithography mask will be imaged into a 2.6×1.65 cm rectangle on the wafer due to the increased reduction factor of the lens’ vertical direction. Layers exposed on high-NA anamorphic scanners will require two stitched halffields to achieve the equivalent exposure area of previous-generation scanners. Stitching strategies will depend on the product type being manufactured. For chips with a large die area, it will be necessary to stitch fields across the die. For smaller chips, it may be advantageous to use three stitched exposures depending on the die size. In any case, the stray light from neighboring fields and black border proximity effects cause challenges for robust manufacturing. Some recent studies have shown that the CD may vary significantly as a function of the proximity to the black border edge due to multilayer stresses. In addition, stitching through a die has increased optical proximity effects which will need to be corrected to achieve the desired wafer CD. In this paper we examine the effects relevant to designing a stitched process, quantify manufacturing tolerances, and show how these effects can be corrected with EDA. More specifically, we examine the optical and mechanical properties of the multi-layer black border etch and optimization of sub-resolution gratings to reduce reflectivity with phase shifting absorber materials. Ultimately, we will show that for a well designed stitch, the effects of stitching can be corrected without impact to process window.

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We investigate the impact on statistical variability induced by random dopant fluctuations (RDF) and gate line edge roughness (LER) acting separately and simultaneously in negative capacitance (NC) FETs. In order to simulate the NCFETs, we couple the 3D transistor simulator tool GARAND which is well suited for statistical variability simulations, with the Landau -Khalatnikov (L-K) model of the ferroelectric. We also explore the impact of ferroelectric thickness scaling.