No abstract

No abstract

A synchronous optical network (SONET) OC-48 32:l and 1:32b multiplexer ( m u ) and demultiplexer (demux) chip set includes a four-phase clocking architecture, a programmable reaawrite, a datahold signal, a current buildup output buffer, and matched output data and clock paths.To minimize the number of high-speed data paths on the m u / demux, a four-phase clocking design is used. The high-speed input clock is immediately divided down by 4, resultingin 4 clocks with a 25% duty cycle. Each rising edge of the clock is 90" out-ofphase from the previous clock. The architecture used to generate these clocks is shown in Figure 1. All internal data paths and control signals are clocked with phases at least 180" out-of-phase with each other. This makes meeting setup times significantly easier. The block diagrams of the mux and demux are shown in Figure 2 and 3 respectively.The mux outputs a differential ECL 2.5GHz clock and an ECL data stream that is retimed to the output clock. The requirements on the output data timing is that the rising edge ofthe output clock shall occur within +50ps of the data bit center. To achieve this timing, the data and clock paths are balanced and the data is clocked on the falling edge of the output clock.A current buildup output buffer ensures adequate output swing for single-ended ac coupled applications. The output buffer consists of 3 stages. The first stage is a 400pA CML buffer. The second stage is a 1mA gate with 3.8mA output followers. The last stage driving the output is an 11.5mA gate. The last stage has a 1.2V output swing at low frequencies to guarantee a greater than 500mV output swing at 2.5GHz. Figure 4.0 shows the schematic of the output buffer driver.To reduce system timing constraints when using the chipset, a programmable writehead signal is provided on the m d d e m u x respectively. On the MUX, three pins are provided to shift the output of the write signal relative to the internal 32b load signal. This allows the write signal to move relative to the internal load with a resolution of l/8 of the load period or 1.6ns for 2.5GHz operation. A similar signal for the demux is used for reading the data from the 32b output word.A test signal, referred to as datahold, is used to indicate the hold time on the chip. This signal is asserted when the internal load signal is generated and deasserted when the data on the 32b bus changes. Thus, the duty cycle of the datahold signal indicates the internal hold time on the chip. The hold time can be manipulated by the controlling system using the programmable write signal discussed above. Through the use of the programmable write signal and the datahold signal, the timing can be optimized for particular system timing constraints. Figure 5 shows the demux chip micrograph. The chip uses an existing bipolar array, thus optimization for speedlpower and minimizing chip area were compromised compared to those of a full-custom design.The chip is housed in a 64-pin quad flat pack with a heat spreader. The mux power dissipation is 0.9W while the d...

No abstract

The paper discusses a novel differential Split Level Bus (SLB) . Using this technique eliminates problems associated with differential bus arbitration, multiple drivers, and the condition where all drivers are disabled.